• ETRI Journal
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• v.35 no.3
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• pp.425-430
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• 2013

In this paper, we propose a triple-gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage ($BV_{DS}$) and on-state current ($I_{D,MAX}$), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer ($SiO_2$) of a conventional RSO power MOSFET is changed to a multilayered insulator ($SiO_2/SiN_x/TEOS$). The inserted $SiN_x$ layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and the poly-Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as $BV_{DS}$ and $I_{D,MAX}$, simulation studies are performed on the function of the gate configurations and their bias conditions. $BV_{DS}$ and $I_{D,MAX}$ are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15-V gate voltage. This $I_{D,MAX}$ variation indicates the specific on-resistance modulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.1-8
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• 2005

A RC parallel gate model is used to consider gate distributed effect that affects RF MOSFET performance, and extraction formula based on $Y_{11}$-parameters are used to extract model parameters directly from measured S-parameters. Better agreement between measured and modeled S-parameters in the frequency range beyond 10 GHz is achieved by using the RC parallel model than conventional Rg one, demonstrating the accuracy of the RC model and extraction technique. Using these extraction methods, gate voltage dependent curves of RC gate model parameters are newly extracted, and these parameter data will greatly contribute to developing a RF nonlinear gate model.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.1-9
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• 1999

Timing-level circuit analyses are used to obtain fast and accurate results, and the analysis of gate and interconnect delay is necessary to validate the correctness of circuit design. This paper proposes an efficient algorithm which simultaneously calculates the gate delay and the transition time of linearized voltage source for subsequent interconnect delay calculation. The notion of effective capacitance is used to calculate the gate delay and the transition time of linearized voltage source which considers the on-resistance of driving gate. The procedure for obtaining the gate delay and the transition time of linearized voltage source has been developed through an iterative operation using the precharacterized data of gates. While previous methods require extra information for the transition time calculation of linearized voltage sources, our method uses the derived data during the gate delay calculation process, which does not require any change in the precharacterization process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.6
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• pp.435-443
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• 2017

In this study, we analyzed the effects of the common-gate transistor bias of a switching mode CMOS power amplifier. Although the most earier works occured on the transistor sizes of the cascode structure, we showed that the gate bias of the common-gate transistor also influences the overall efficiency of the power amplifier. To investigate the effect of the gate bias, we analyzed the DC power consumption according to the gate bias and hence the efficiency of the power amplifier. From the analyzed results, the optimized gate bias for the maximum efficiency is lower than the supply voltage of the power amplifier. We also found that an excessively low gate bias may degrade the output power and efficiency owing to the effects of the on-resistance of the cascode structure. To verify the analyzed results, we designed a 1.9 GHz switching mode power amplifier using $0.18{\mu}m$ RF CMOS technology. As predicted in the analysis, the maximum efficiency is obtained at 2.5 V, while the supply voltage of power amplifier is 3.3 V. The measured maximum efficiency is 31.5 % with an output power of 29.1 dBm. From the measureed results, we successfully verified the analysis.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.208-211
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• 1999

Abstract - Electrical characteristics or asymmetric n-MOSFET's with different source and drain geometry are experimently investigated using test structures having various gate width. Saturation drain current and resistance in linear region are estimated by a simple schematic model, which consists of conventional device having parasitic resistor. A comparison of experimental results of symmetric and asymmetric devices gives the parasitic resistance caused by abnormal device structure. The suggested model shows good agreement with the measured drain current for both forward- and reverse-modes.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.55-59
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• 2013

A new method using RF Ids determined from measured S-parameters is proposed to extract the gate-voltage dependent effective carrier velocity of bulk MOSFETs in the saturation region without additional dc Ids measurement data suffering parasitic resistance effect that becomes larger with continuous down-scaling to sub-$0.1{\mu}m$. This method also allows us to extract the carrier velocity in the saturation region without the difficult extraction of bias-dependent parasitic gate-source capacitance and effective channel length. Using the RF technique, the electron velocity overshoot exceeding the bulk saturation velocity is observed in bulk N-MOSFETs with a polysilicon gate length of $0.065{\mu}m$.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.315-318
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• 1999

We have proposed and fabricated the new bottom-gated polycrystalline silicon (poly-Si) thin film transistor (TFT) with a partial amorphous-Si region by employing the selective laser annealing. The channel layer of the proposed TFTs is composed of poly-Si region in the center and a-Si region in the edge. The TEM image shows that the local a-Si region is successfully fabricated by the effective cut out of the incident laser light in the upper a-Si layer. Our experimental results show that the ON/OFF current ratio is increased significantly by more than three orders in the new poly-Si TFT compared with conventional poly-Si TFT. The leakage current is decreased significantly due to the highly resistive a-Si re TFTs while the ON-series resistance of the local a-Si is reduced significantly due to the considerable inducement of electron carriers by the positive gate bias, so that the ON-current is not decreased much.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.395-395
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• 2007

We report on the fabrication of soluble pentacene-based thin-film transistors (TFTs) that consist of $NiO_x$, poly-vinyl phenol (PVP), and Ni for the source-drain (SID) electrodes, gate dielectric, and gate electrode, respectively. The $NiO_x$ SID electrodes of which the work function is well matched to that of soluble pentacene are deposited on a soluble pentacenechannel by sputter deposited of NiO powder and show a moderately low but still effective transmittance of ~65% in the visible range along with a good sheet resistance of ${\sim}40{\Omega}/{\square}$. The maximum saturation current of our soluble pentacene-based TFT is about $15{\mu}A$ at a gate bias of -40showing a high field effect mobility of $0.06cm^2/Vs$ in the dark, and the on/off current ratio of our TFT is about $10^4$. It is concluded that jointly adopting $NiO_x$ for the S/D electrodes and PVP for gate dielectric realizes a high-quality soluble pentacene-based TFT.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.491-491
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• 2011

Transparent and flexible electronic devices that are light-weight, unbreakable, low power consumption, optically transparent, and mechanical flexible possibly have great potential in new applications of digital gadgets. Potential applications include transparent displays, heads-up display, sensor, and artificial skin. Recent reports on transparent and flexible field-effect transistors (tf-FETs) have focused on improving mechanical properties, optical transmittance, and performances. Most of tf-FET devices were fabricated with transparent oxide semiconductors which mechanical flexibility is limited. And, there have been no reports of transparent and flexible all-organic tf-FETs fabricated with organic semiconductor channel, gate dielectric, gate electrode, source/drain electrode, and encapsulation for sensor applications. We present the first demonstration of transparent, flexible all-organic sensor based on multifunctional organic FETs with organic semiconductor channel, gate dielectric, and electrodes having a capability of sensing infrared (IR) radiation and mechanical strain. The key component of our device design is to integrate the poly(vinylidene fluoride-triflouroethylene) (P(VDF-TrFE) co-polymer directly into transparent and flexible OFETs as a multi-functional dielectric layer, which has both piezoelectric and pyroelectric properties. The P(VDF-TrFE) co-polumer gate dielectric has a high sensitivity to the wavelength regime over 800 nm. In particular, wavelength variations of P(VDF-TrFE) molecules coincide with wavelength range of IR radiation from human body (7000 nm ~14000 nm) so that the devices are highly sensitive with IR radiation of human body. Devices were examined by measuring IR light response at different powers. After that, we continued to measure IR response under various bending radius. AC (alternating current) gate biasing method was used to separate the response of direct pyroelectric gate dielectric and other electrical parameters such as mobility, capacitance, and contact resistance. Experiment results demonstrate that the tf-OTFT with high sensitivity to IR radiation can be applied for IR sensors.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.808-812
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• 2006

In this dissertation, Ru-Zr metal gate electrode deposited on two kinds of dielectric were formed for MOS capacitor. Sample co-sputtering method was used as a alloy deposition method. Various atomic composition was achieved when metal film was deposited by controlling sputtering power. To study the characteristics of metal gate electrode, C-V(capacitance-voltage) and I-V(current-voltage) measurements were performed. Work function and equivalent oxide thickness were extracted from C-V curves by using NCSU(North Carolina State University) quantum model. After the annealing at various temperature, thermal/chemical stability was verified by measuring the variation of effective oxide thickness and work function. This dissertation verified that Ru-Zr gate electrodes deposited on $SiO_{2}\;and\;ZrO_{2}$ have compatible work functions for NMOS at the specified atomic composition and this metal alloys are thermally stable. Ru-Zr metal gate electrode deposited on $SiO_{2}\;and\;ZrO_{2}$ exhibit low sheet resistance and this values were varied with temperature. Metal alloy deposited on two kinds of dielectric proposed in this dissertation will be used in company with high-k dielectric replacing polysilicon and will lead improvement of CMOS properties.