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http://dx.doi.org/10.5515/KJKIEES.2017.28.6.435

Analysis of the Gate Bias Effects of the Cascode Structure for Class-E CMOS Power Amplifier  

Seo, Donghwan (The 8th R&D Institute, Agency for Defense Developement)
Publication Information
The Journal of Korean Institute of Electromagnetic Engineering and Science / v.28, no.6, 2017 , pp. 435-443 More about this Journal
Abstract
In this study, we analyzed the effects of the common-gate transistor bias of a switching mode CMOS power amplifier. Although the most earier works occured on the transistor sizes of the cascode structure, we showed that the gate bias of the common-gate transistor also influences the overall efficiency of the power amplifier. To investigate the effect of the gate bias, we analyzed the DC power consumption according to the gate bias and hence the efficiency of the power amplifier. From the analyzed results, the optimized gate bias for the maximum efficiency is lower than the supply voltage of the power amplifier. We also found that an excessively low gate bias may degrade the output power and efficiency owing to the effects of the on-resistance of the cascode structure. To verify the analyzed results, we designed a 1.9 GHz switching mode power amplifier using $0.18{\mu}m$ RF CMOS technology. As predicted in the analysis, the maximum efficiency is obtained at 2.5 V, while the supply voltage of power amplifier is 3.3 V. The measured maximum efficiency is 31.5 % with an output power of 29.1 dBm. From the measureed results, we successfully verified the analysis.
Keywords
CMOS; RF Power Amplifier; Cascode; Common-gate; Gate Bias;
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