• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.2
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• pp.49-53
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• 2005

The current drive in a MOSFET is limited by the intrinsic channel resistance. All other parasitic elements in a device structure perform significant functions leading to degradation in the device performance. These other resistances must be less than 10$\%$-20$\%$ of the channel resistance. To meet the necessary requirements, the methodology of separation and quantification of those resistances should be investigated. In this paper, we developed an extraction method for the resistances using calibrated TCAD simulation. The resistance of the extension region is also partially determined by the formation of a surface accumulation region that gathers below the gate in the tail region of the extension profile. This resistance is strongly affected by the abruptness of the extension profile because the steeper the profile is, the shorter this accumulation region will be.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.9
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• pp.605-610
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• 1999

An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with a recessed source structure is proposed to improve the on-resistance and the breakdown voltage. The recessed source structure can decrease the on-resistance by reducing the path of electron current, also increase the breakdown voltage by extending the effective length of gate field plate. Simulation results by TSUPREM4 and MEDICI have shown that the on-resistance of the LDMOS with a recessed source was 26% lower than conventional LDMOS. The breakdown voltage of proposed device was found to be 45V while that of conventional device was 36.5 V. At the same breakdown voltage of 36.5V, the on-resistance of the LDMOS with a recessed source was 41% lower than that of conventional structure.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.70-70
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• 2009

In this paper, we proposed 2500V Non punch-through(NPT) Insulated gate bipolar transistor(IGBT) for high voltage industry application. we carried out optimal simulation for high efficiency of 2500V NPT IGBT according to size of device. In results, we obtaind design parameter with 375um n-drift thickness, 15um gate length, and 8um emitter windows. After we simulate with optimal parameter, we obtained 2840V breakdown voltage and 3.4V Vce,sat. These design and process parameter will be used designing of more 2000V NPT IGBT devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.1
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• pp.23-28
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• 2008

In this paper, transient characteristics of the Punch Through Insulated Gate Bipolar Transistor (PT-IGBT) have been studied. On the contrary to Non-Punch Through Insulated Gate Bipolar Transistor(NPT-IGBT), it has a buffer layer and reduces switching power loss. It has a simple drive circuit controlled by the gate voltage of the MOSFET and low on-state resistance of the bipolar junction transistor. The transient characteristics of the PT-IGBT have been analyzed analytically. Excess minority carrier and charge distribution in active base region, the rate of anode voltage with time are expressed analytically by adding the influence of buffer layer. The experimental data is obtained from manufacturer. The theoretical predictions of the analysis have been compared with the experimental data obtained from the measurement of a device(600 V, 15 A) and show good agreement.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.273-279
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• 2010

In this paper, we proposed 2500 V Non punch-through(NPT) Insulated gate bipolar transistor(IGBT) for high voltage industry application. we carried out optimal simulation for high efficiency of 2500 V NPT IGBT according to size of device. In results, we obtaind design parameter with 375 um n-drift thickness, 15 um gate length, and 8um emitter windows. After we simulate with optimal parameter, we obtained 2840 V breakdown voltage and 3.4V Vce,sat. These design and process parameter will be used designing of more 2000 V NPT IGBT devices.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.13-16
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• 2002

In this study, the electrical characteristics of 100v-Class LDMOSFET for high temperature applicat -ions such as electronic control systems of automo -biles and motor driver were investigated. Measurement data are taken over wide range of temperature(300k-SOOK) and various gate length(1.5 #m-3.0#m, step 0.3). In high temperature condition(>500k), drain current decreased over 30%, and specific on- resistance increased about three times in comparison with room temperature. Moreover, the ratio ROJBV, a figure of merit of the device, increased with increasing temperature.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.683-686
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• 2003

In this paper, we have investigated electrical characteristics of TRENCH GATE POWER MOSFET in the temperature range of 300K to 500K. The results of this study indicate that on-resistance and breakdown voltage increase with the temperature ,but drain current, threshold voltage and transconductance decrease with the temperature. Especially, it is observed that electrical characteristics are improved as numerical unit cells are increased.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.7
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• pp.557-562
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• 2000

160nm thick amorphous Si and polycrystalline Si were each deposited on to 10nm thick SiO$_2$, Co monolayer and Co/Ti bilayer were sequentially evaporated to form Co-polycide. Then MOS capacitors were fabricated by BF$_2$ ion-implantation. The characteristics of the fabricated capacitor samples depending upon the drive-in annel conductions were measured to study the effects of thermal stability of CoSi$_2$and dopant redistribution on electrical properties of Co-polycide gates. Results for capacitors using Co/Ti bilayer and drive-in annealed at 80$0^{\circ}C$ for 20~40sec. showed excellent C-V characteristics of gate electrode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.25-28
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• 2000

In this study, Transient Characteristics of the Punch-Through Insulated Gate Bipolar Transistor (PT-IGBT) has been studied. On the contraty to Non-Punch Through Insulated Gate Bipolar Transistor(NPT-IGBT), PT-IGBT has buffer layer It has a simple drive circuit controlled by the gate voltage of the MOSFET and the low on-state resistance of the bipolar junction transistor. In this paper, the transient characteristics with temperature of the PT-IGBT has been analyzed analytically. PT-IGBT is made to reduce switching power loss. Excess Minority carrier distribution inactive base region and base charge, the rate of voltage with time is expressed analytically to include buffer layer.

• Transactions on Electrical and Electronic Materials
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• v.17 no.4
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• pp.222-226
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• 2016

This paper investigated the trench process, unified field limit ring, and other products for the development of a 500 V-level unified trench gate power MOSFET. The optimal base chemistry for the device was found to be SF₆. In SEM analysis, the step process of the trench gate and field limit ring showed outstanding process results. After finalizing device design, its electrical characteristics were compared and contrasted with those of a planar device. It was shown that, although both devices maintained a breakdown voltage of 500 V, the Vth and on-state voltage drop characteristics were better than those of the planar type.