The Transactions of the Korean Institute of Electrical Engineers C (대한전기학회논문지:전기물성ㆍ응용부문C)

The Korean Institute of Electrical Engineers (대한전기학회)
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Numerical Analysis of a SOI LDMOS with a Recessed Source for Low ON Resistance

ON 저항이 작은 Recessed Source 구조 SOI LDMOS의 수치해석

  • 양회윤 ((주) 아이티엠비 IP 사업팀 연구원) ;
  • 김성룡 (아주대 대학원) ;
  • 최연익 (아주대 공대 전자공학부)
  • Published : 1999.09.01
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Abstract

An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with a recessed source structure is proposed to improve the on-resistance and the breakdown voltage. The recessed source structure can decrease the on-resistance by reducing the path of electron current, also increase the breakdown voltage by extending the effective length of gate field plate. Simulation results by TSUPREM4 and MEDICI have shown that the on-resistance of the LDMOS with a recessed source was 26% lower than conventional LDMOS. The breakdown voltage of proposed device was found to be 45V while that of conventional device was 36.5 V. At the same breakdown voltage of 36.5V, the on-resistance of the LDMOS with a recessed source was 41% lower than that of conventional structure.

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References

  1. IEEE Trans. on Electron Devices v.38 A 100V lateral LDMOS transistor with a 0.3㎛ channel in a 1㎛ Silicon Film on Insulator on Silicon U. Apel(et al.)
  2. SSDM Extended Abstracts Device simulation of a thin-film SOI power LDMOSFET for structure optimization S. Matsumoto(et al.)
  3. IEDM Tech. Dig. A novel LDMOS structure with a step gate oxide D. G. Lin(et al.)
  4. TMA User's Manual Two-dimensional process simulation program SUPREM4
  5. TMA User's Manual Two-dimensional device simulation program MEDICI