• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 D
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• pp.1965-1967
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• 1999

We have investigated the electrical characteristics of the poly-Si TFT's with the novel gate insulator structure. The gate insulator makes the offset region to reduce leakage current, and the electrical characteristics are obtained by employing Virtual Wafer Fab. simulator. As increases the gate insulator thickness above the offset region of this structure from $0{\AA}$ to $2000{\AA}$, the OFF state current at $V_G$=10V decrease by two orders in magnitude while ON state current doesn't decrease significantly. ON/OFF current ratios for conventional device and the proposed device with $2000{\AA}$ gate insulator thickness are $1.68{\times}10^5$ and $1.07{\times}10^7$, respectively.

• 대한전자공학회논문지
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• 제27권12호
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• pp.1841-1851
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• 1990

Self-aligned gate GaAs MESFETs using ion beam deposited tungsten applicable to GaAs LSI fabrication process have been fabricated. Silicon implanted samples were annealed using isothermla two step RTA process and conventional one step RTA process. The electrical and physicla characteristics of annealed samples were investigated using Hall and I-V measurements. As results of measurements, activation characteristics of the isothermal two step RTA process are better than those of one step annealed ones. Using the developed processes, GaAs SAFETs (Self-Aligned Gate FET) have been fabricated and electdrical characteirstics are measured. As results, subthreshold currents of SAGFETs are 6x10**-10 A/\ulcorner, that is compatible to conventional MESFET, maximum transconductances of 0.75\ulcorner gate MESFET using one step RTA process and 2\ulcorner gate MESFET using isothermal two step RTA process are 18 mS/mm, 41 mS/mm respectively.

• 전기전자학회논문지
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• 제22권2호
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• pp.484-487
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• 2018

5 MeV proton-irradiation with total dose of $10^{15}/cm^2$ was performed on AlGaN/GaN-on-Si high electron mobility transistors (HEMTs) with various gate metals including Ni, TaN, W, and TiN to investigate the degradation characteristics. The positive shift of pinch-off voltage and the reduction of on-current were observed from irradiated HEMTs regardless of a type of gate materials. Hall and transmission line measurements revealed the reduction of carrier mobility and sheet charge concentration due to displacement damage by proton irradiation. The shift of pinch-off voltage was dependent on Schottky barrier heights of gate metals. Gate leakage and capacitance-voltage characteristics did not show any significant degradation demonstrating the superior radiation hardness of Schottky gate contacts on GaN.

• 대한전자공학회논문지SD
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• 제40권6호
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• pp.379-383
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• 2003

Double-Gate MOSFET의 TSi변화에 따른 subthreshold 특성을 비교 분석하였다. Lightly-doped asymmetrical 소자의 경우에 symmetrical 소자에 비하여 subthreshold current가 TSi에 따라 급격하게 증가하는 현상을 발견하였으며 이는 낮은 depletion charge 때문에 TSi내의 전압분포가 linear한 특성을 갖는 것에 기인함을 밝혔다. 또한 이러한 현상을 설명할 수 있는 analytical equation을 유도하였으며 analytical equation 결과와 device simulation 결과를 비교하여 그 정확도를 검증하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 연구회
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• pp.148-152
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• 2001

One set of MMIC library has been developed using gate recess etching by spin processor. It is superior than that of dipping Method in the uniformity and the reproducibility of gate recess. A DC characteristics of p-HEMT have a uniform characteristics in the whole wafer than that of dipping method. The low noise p-HEMT with the $0.6{\mu}m$ and $200{\mu}m$ of gate length and gate width, respectivily, has a uniform characteristics of Idss 130~145 mA, conductances 190~220mS/nm, and threshold voltage -0.7~-1.1V in the drain voltage of 2V.

• 한국전기전자재료학회논문지
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• 제31권2호
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• pp.74-79
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• 2018

In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.

• 전기전자학회논문지
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• 제25권2호
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• pp.350-355
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• 2021

IGBT는 MOSFET과 BJT의 구조를 동시에 포함하고 있는 전력반도체 소자이며, MOSFET의 빠른 스위칭 속도와 BJT의 고 내압, 높은 전류내량 특성을 갖고 있다. GBT는 높은 항복전압, 낮은 V_CE-SAT, 빠른 스위칭 속도, 고 신뢰성의 이상적인 파워 반도체 소자의 요구사항을 목표로 하는 소자이다. 본 논문에서는 1,200V 급 Trench Gate Field Stop IGBT의 상단 공정 파라미터인 Gate oxide thickness, Trench Gate Width, P+ Emitter width를 변화시키면서 변화하는 Eoff, V_CE-SAT을 분석하였고, 이에 따른 최적의 상단 공정 파라미터를 제시하였다. Synopsys T-CAD Simulator를 통해 항복전압 1,470V와 V_CE-SAT 2.17V, Eon 0.361mJ, Eoff 1.152mJ의 전기적 특성을 갖는 IGBT 소자를 구현하였다.

• 한국정보통신학회논문지
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• 제7권2호
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• pp.263-268
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• 2003

본 논문에서는 main gate(MG)와 side gate(SG)를 갖는 double gate(DG) MOSFET 구조를 조사하였다. MG가 50nm일 때 최적의 SG 전압은 약 3V임을 알 수 있었고, 각각의 MG에 대한 최적의 SG 길이는 약 70nm임을 알 수 있었다. DG MOSFET는 매우 작은 문턱 전압 roll-off 특성을 나타내고, 전류-전압 특성곡선에서 VMG=VDS=1.5V, VSG=3V인 곳에서 포화전류는 550$\mu\textrm{A}$/m임을 알 수 있었다. subthrehold slope는 82.6㎷/decade, 전달 컨덕턴스는 l14$\mu\textrm{A}$/$\mu\textrm{m}$ 그리고 DIBL은 43.37㎷이다 다중 입력 NAND 게이트 로직 응용에 대한 이 구조의 장점을 조사하였다. 이때, DG MOSFET에서 41.4GHz의 매우 높은 컷오프 주파수를 얻을 수 있었다.

• E2M - 전기 전자와 첨단 소재
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• 제7권5호
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• pp.376-382
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• 1994

In this study we developed a program(DEVSIM) to simulate the two dimensional distribution of the electrostatic potential and the electric field of the arbitrary structure consisting of GaAs/AlGaAs semiconductor and metal as well as dielectric. By the comparision of the electric field distribution of GaAs MESFETs with the various recess gates we proposed a suitable device structure to improve the breakdown characteristics of MESFET. According to the results of simulation the breakdown characteristics were improved as the thickness of the active epitaxial layer was decreased. And the planar structure, which had the highly doped layer under the drain for the ohmic contact, was the worst because the highly doped layer prevented the space charge layer below the gate from extending to the drain, which produced the narrow spaced distribution of the electrostatic potential contours resulting in the high electric field near the drain end. Instead of the planar structure with the highly doped drain the recess gate structure having the highly doped epitaxial drain layer show the better breakdown characteristics by allowing the extention of the space charge layer to the drain. Especially, the structure in which the part of the drain epitaxial layer near the gate show the more improvement of the breakdown characteristics.

• 전자공학회논문지A
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• 제31A권1호
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• pp.77-83
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• 1994

Characteristics of hot-electron-induced degradation by AC, DC was investigated for p-MOSFET's(W/L=25/l$\mu$m) with sub-10nm RTP-CVD gate oxides. It was confirmed that the surface channel p-MOSFET of a thinner gate oxide shows less degradation. Mechanisms for this effect were analyzed using a simple MOS Device degradation model. It was found that the number of generated electron traps(fixed charge) is determined by the amount of peak gate current, dependent of the gate oxide thickness, and the major cause of the smaller degradation in the thinner gate oxide devices is the lower hot electron trapping carriers.