Analysis of Anomalous Subthreshold Characteristics in Ligtly-Doped Asymmetric Double-Gate MOSFETs

Asymmetric Double-Gate MOSFET의 Subthreshold 특성 분석

  • 이혜림 (이화여자대학교 정보통신학과) ;
  • 신형순 (이화여자대학교 정보통신학과)
  • Published : 2003.06.01

Abstract

The subthreshold characteristics of Double-Gate MOSFETs are analyzed for various Tsi. In the lightly-doped asymmetric device, it is found that the subthreshold current dramatically increases as the Tsi increases and this phenomenon is due to the linear distribution of potential in the channel region with low depletion-charge. Further, we derived an analytical equation which can explain this phenomenon and verified the accuracy of analytical equation by comparing with the result of device simulation.

Double-Gate MOSFET의 TSi변화에 따른 subthreshold 특성을 비교 분석하였다. Lightly-doped asymmetrical 소자의 경우에 symmetrical 소자에 비하여 subthreshold current가 TSi에 따라 급격하게 증가하는 현상을 발견하였으며 이는 낮은 depletion charge 때문에 TSi내의 전압분포가 linear한 특성을 갖는 것에 기인함을 밝혔다. 또한 이러한 현상을 설명할 수 있는 analytical equation을 유도하였으며 analytical equation 결과와 device simulation 결과를 비교하여 그 정확도를 검증하였다.

Keywords

References

  1. F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, 'Double-gate silicon-on-insulator transistor with volume inversion : A new device with greatly enhanced perfor-mance,' IEEE Electron Device Lett., vol. EDL-8, pp. 410, 1987
  2. R. H. Yan, A. Ourmazd, and K. F. Lee, 'Scaling the Si MOSFET : From bulk to SOI to bulk,' IEEE Trans. Electron Devices, vol. 39, pp. 1704-1710, 1992 https://doi.org/10.1109/16.141237
  3. K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, 'Scaling theory for double-gate MOSFETs,' IEEE Trans. Electron Devices, vol. 40, pp. 2326-2339, 1993 https://doi.org/10.1109/16.249482
  4. Y. Taur, 'Analytic solution of charge and capacitance in symmetric and asymmetric Double-Gate MOSFETs', IEEE Trans. Electron Devices, vol. 48, pp. 2861-2869, 2001 https://doi.org/10.1109/16.974719
  5. T. Tanaka, H. Horie, S. Ando and S. Hijiya, 'Analysis of P+ poly Si Double-Gate thin-film SOI MOSFETS,' IEDM Tech. Dig., pp. 683, 1991 https://doi.org/10.1109/IEDM.1991.235330
  6. K. Kim and J.G. Fossum, 'Double-Gate CMOS: Symmetrical-Versus Asymmetrical-Gate Devices', IEEE Trans. Electron Devices, vol. 48, pp. 294-299, 2001 https://doi.org/10.1109/16.902730
  7. MEDICI V.1999.2, Fremont : Avant!, 1999
  8. S. Venkatesan, G. W. Neudeck, R. F. Pierret, 'Dual Gate operation and volume inversion in n-Channel SOI MOSFET's,' IEEE Electron Device Lett., vol. 13, pp. 44-46, 1992 https://doi.org/10.1109/55.144946