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http://dx.doi.org/10.4313/JKEM.2018.31.2.74

Effects of Doping Concentration of Polycrystalline Silicon Gate Layer on Reliability Characteristics in MOSFET's  

Park, Keun-Hyung (College of Electrical & Computer Engineering, Chungbuk National University)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.31, no.2, 2018 , pp. 74-79 More about this Journal
Abstract
In this report, the results of a systematic study on the effects of polycrystalline silicon gate depletion on the reliability characteristics of metal-oxide semiconductor field-effect transistor (MOSFET) devices were discussed. The devices were fabricated using standard complimentary metal-oxide semiconductor (CMOS) processes, wherein phosphorus ion implantation with implant doses varying from $10^{13}$ to $5{\times}10^{15}cm^{-2}$ was performed to dope the polycrystalline silicon gate layer. For implant doses of $10^{14}/cm^2$ or less, the threshold voltage was increased with the formation of a depletion layer in the polycrystalline silicon gate layer. The gate-depletion effect was more pronounced for shorter channel lengths, like the narrow-width effect, which indicated that the gate-depletion effect could be used to solve the short-channel effect. In addition, the hot-carrier effects were significantly reduced for implant doses of $10^{14}/cm^2$ or less, which was attributed to the decreased gate current under the gate-depletion effects.
Keywords
MOSFET; Reliability; Gate depletion effect;
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