• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.12-15
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• 2022

In this study, we studied the effects of transfer gate on the photocurrent characteristics of gate/body-tied (GBT) metal-oxide semiconductor field-effect transistor (MOSFET)-type photodetector. The GBT MOSFET-type photodetector has high sensitivity owing to the amplifying characteristic of the photocurrent generated by light. The transfer gate controls the flow of photocurrent by controlling the barrier to holes, thereby varying the sensitivity of the photodetector. The presented GBT MOSFET-type photodetector using a built-in transfer gate was designed and fabricated via a 0.18-㎛ standard complementary metal-oxide-semiconductor (CMOS) process. Using a laser diode, the photocurrent was measured according to the wavelength of the incident light by adjusting the voltage of the transfer gate. Variable sensitivity of the presented GBT MOSFET-type photodetector was experimentally confirmed by adjusting the transfer gate voltage in the range of 405 nm to 980 nm.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.4
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• pp.253-260
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• 2012

IGBT (insulated gate bipolar transistor) have received wide attention because of their high current conduction and good switching characteristics. To reduce the power loss of IGBT, the on state voltage drop should be lowered and the switching time should be shorted. However, there is Trade-off between the breakdown voltage and the on state voltage drop. To achieving good electrical characteristics, field stop IGBT (FS IGBT) is proposed. In this paper, 1,200 V planar gate non punch-through IGBT (planar gate NPT IGBT), planar gate FS IGBT and trench gate FS IGBT is designed and optimized. The simulation results are compared with each three structures. In results, we optain optimal design parameters and confirm excellence of trench gate FS IGBT. Experimental result by using medici, shows 40% improvement of on state voltage drop.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.970-973
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• 1999

When the size of the device is decreased, the hot carrier degradation presents a severe problem for long-term device reliability. In this paper we fabricated & tested the 0.26${\mu}{\textrm}{m}$ NMOSFET with wet gate oxide and nitride oxide gate to compare that the characteristics of hot carrier effect, charge to breakdown, transistor Id_Vg curve and charge trapping using the Hp4145 device tester As a result we find that the characteristics of nitride oxide gate device better than wet gate oxide device, especially a hot carrier lifetime(nitride oxide gate device satisfied 30years, but the lifetime of wet gate oxide was only 0.1year), variation of Vg, charge to breakdown and charge trapping etc.

• Journal of The Korean Society of Agricultural Engineers
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• v.46 no.2
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• pp.41-47
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• 2004

A model test is carried out to investigate flow-induced vibration of a Tainter gate in estuary sulices. The gate model scaled with the ratio of 1:25 is made of acryl panel dimensioned 0.66 m in width, 0.5 m in height in the concrete test flume. Firstly, natural frequencies of the model gate are measured and the results are compared with the numerical results in order to verify the model. In the flow from the gate inside to the gate outside, the amplitudes of the vibration are measured under the different gate opening and downstream water level conditions. Also revised gate models with 20 mm bottom width are tested under the different gate openings and water levels. The results are analyzed to study the characteristics of the Tainter gate vibration in the sea ward flow. These test results are assessed in comparison with the results in the lake ward flow, as a result, presents the dynamic characteristics of the Tainter gate and a basic data for the guide manuals of gate management.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.54-61
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• 2011

In this paper, a simple analytical model for deriving the I-V characteristics of a cylindrical surrounding gate SOI MOSFET with intrinsic silicon core is suggested. The Poisson equation in the intrinsic silicon core and the Laplace equation in the gate oxide layer are solved analytically. The surface potentials at both source and drain ends are obtained by means of the bisection method. From them, the surface potential distribution is used to describe the I-V characteristics in a closed-form. Simulation results seem to show the dependencies of the I-V characteristics on the various device parameters and applied bias voltages within a range of satisfactory accuracy.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.490-493
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• 2002

In this study, we have investigated optimum value for side gate length and side gate voltage of double gate (DG) MOSFET with main gate and side gate. We know that optimum side gate voltage for each side length is about 3V. Also, we know that optimum side gate length for each main gate length is about 70nm. We have presented the transconductance and subthreshold slope for each side gate length. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.88-92
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• 2010

Bottom gate and top gate field-effect transistor based carbon nanotube(CNT) were fabricated by CMOS process. Carbon nanotube directly grown by thermal chemical vapor deposition(CVD) using Ethylene ($C_2H_4$) gas at $700^{\circ}C$. The growth properties of CNTs on the device were analyzed by SEM and AFM. The electrical transport characteristics of CNT FET were investigated by I-V measurement. Transport through the nanotubes is dominated by holes at room temperature. By varying the gate voltage, bottom gate and top gate field-effect transistor successfully modulated the conductance of FET device.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.204-209
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• 2017

We have investigated a Mo/Au gate scheme for use in AlGaN/GaN-on-Si HFETs. AlGaN/GaN-on-Si HFETs were fabricated with Ni/Au or Mo/Au gates and their electrical characteristics were compared after thermal stress tests. While insignificant difference was observed in DC characteristics, the Mo/Au gate device exhibited lower on-resistance with superior pulsed characteristics in comparison with the Ni/Au gate device.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1101-1104
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• 2003

In this paper, we analyzed the gate current and substrate current by the hot carrier effects and restoration phenomenon of characteristics by time in the p-channel MOSFETs. The Stress voltage condition is a voltage in maximum gate current and time is 3s, 10s, 30s, l00s, 1000s, 2000s and 3000s. As results of analysis, the gate current and substrate current were decreased by stress time, and the restoration time of characteristics were shown the results that were decreased by the exponential times.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.461-463
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• 1999

In this paper, we have systematically investigated the variation of electrical characteristics with back-gate bias of n-channel SOI MOSFET\\`s. When positive bias is applied back-gate surface is inverted and back channel current is increased. When negative bias is applied back-gate surface is accumulated but it does not affect to the electrical characteristics.