• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.4
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• pp.49-55
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• 2015

The inaccuracy of the bias-dependent gate-drain overlap capacitance $C_{gdo}$ simulation in original BSIM4 and BSIM4 macro model using a diode is analyzed in detail. It is found that the accuracy of the macro model is better than of the BSIM4. However, the macro model cannot be used in the linear region. In order to remove the inaccuracy of the conventional models, a new BSIM4 macro model with a physical bias-dependent $C_{gdo}$ equation is proposed and its accuracy is validated in the full bias range.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.10
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• pp.1-8
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• 2002

C- V method is a means to determine the effective channel length for miniaturized MOSFET's. This method achieves L$_{eff}$ by extracting a unique channel length independent extrinsic overlap length($\Delta$L) at a critical gate bias point. In this paper, we conducted an experiment on two different C-V methods. L$_{eff}$ extracted from experiment is compared with L$_{eff}$ simulated from a two-dimensional (2-D) device simulator, and the accuracy of C-V method for L$_{eff}$ extraction is analyzed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.130-133
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• 2011

A comparative study of two capacitance methods to measure the effective channel length in deep-submicron MOSFETs has been made in detail. Since the reduction of the overlap capacitance in the accumulation region is smaller than the addition of the inner fringe capacitance at zero gate voltage, the capacitance method removing the parasitic capacitance in the accumulation region extracts a more accurate effective channel length than the method removing that at zero gate voltage.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.7
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• pp.462-469
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• 1987

A metal gate MOSFET with source/drain regions self-aligned to gate region is proposed. The proposed MOS transistor is fabricated by utilizing the higher oxidation rate of source/drain regions with high doping concentration when compared with channel region with moderate doping. The thick oxide on the source/drain regions reduces the gate and drain(source) overlap capacitance down to that of a self-aligned polysilicon gate device while allowing the use of a metal gate with much lower resistivity than the more commonly used polycrystalline silicon. A ring oscillator composed of 15 inverter stages has been computer simulated using SPICE. The results of the simulation show good agreement with experimental measurement confirming the fast switching speed of propesed MOSFET.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1292-1294
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• 1993

This paper proposes a new structure of polycrystalline silicon(poly-Si) thin film transistor(TFT) having a thick gate-oxide below the gate edge. The new structure is fabricated by the gate re-oxidation in wet ambient. It is shown that the thick gate-oxide below the gate edge is effective in reducing the leakage current and the gate-drain overlap capacitance. We have simulated this device by using the SSUPREM4 process simulator and the SPISCES-2B device simulator. As a simulation result it is found that the new structure provides a low tentage current less than 0.2 pA and achieves a on/off ratio as high as $5{\times}10^7$.

• Journal of IKEEE
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• v.16 no.4
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• pp.283-289
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• 2012

In this paper, We proposed Separate Gate Technique(SGT) to improve the switching characteristics of Trench power MOSFET. Low gate-to-drain 전하 (Miller 전하 : Qgd) has to be achieved to improve the switching characteristics of Trench power MOSFET. A thin poly-silicon deposition is processed to form side wall which is used as gate and thus, it has thinner gate compared to the gate of conventional Trench MOSFET. The reduction of the overlapped area between the gate and the drain decreases the overlapped charge, and the performance of the proposed device is compared to the conventional Trench MOSFET using Silvaco T-CAD. Ciss(input capacitance : Cgs+Cgd), Coss(output capacitance : Cgd+Cds) and Crss(reverse recovery capacitance : Cgd) are reduced to 14.3%, 23% and 30% respectively. To confirm the reduction effect of capacitance, the characteristics of inverter circuit is comprised. Consequently, the reverse recovery time is reduced by 28%. The proposed device can be fabricated with convetional processes without any electrical property degradation compare to conventional device.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.7
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• pp.500-505
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• 2012

In this study, the influence of the intermolecular distance on the charge mobility in a pentacene thin-film was investigated. In order to increase the mobility which depends on the ${\pi}$-overlap between molecules, the intermolecular distance was shortened by compressive force along the conduction channel. Pentacene thin-film was fabricated on flexible substrates bent outward at different radii to stretch the gate dielectric surface and then the substrates were unbent, producing the compressive force to the film. The result showed that the mobility increased proportionally to the strain applied during the pentacene deposition and the molecular packing inside a grain was not optimal for the charge transport.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1549-1551
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• 2002

현재 게이트 길이가 100nm 이하의 MOSFET 소자를 구현할 때 가장 대두되는 문제인 short channel effect를 억제하는 방법으로 제안된 소자 중 하나가 double gate (DG) silicon-on-insulator (SOI) MOSFET이다. 그러나 DG SOI MOSFET는 두 게이트간의 align과 threshold voltage control 문제가 있다. 본 논문에서는 DG SOI MOSFET에서 이상적으로 게이트가 align된 구조와 back 게이트가 front 게이트보다 긴 non-align된 구조가 subthreshold 동작 영역에서 impact ionization에 미치는 영향에 대해 시뮬레이션을 통하여 비교 분석하였다. 그 결과 게이트가 이상적으로 align된 구조보다 back 게이트가 front 게이트보다 긴 non-align된 구조가 게이트와 드레인이 overlap된 영역에서 impact ionization이 증가하였으며 게이트가 각각 n+ 폴리실리콘과 p+ 폴리실리콘을 가진 소자에서 두 게이트가 같은 work function을 가진 소자보다 높은 impact generation rate을 가짐을 알 수 있었다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.12
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• pp.77-87
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• 1993

PMOSFETs were studied on the effect of Hot-Carrier induced drain leakage current (Gate-Induced-Drain-Leakage). The result turned out that change in Vgl(drain voltage where 1pA/$\mu$m of drain leadage current flows) was largest in the Channel-Hot-Hole(CHH) injection condition and next was in dynamic stress and was smallest in electron trapping (Igmax) condition under various stress conditions. It was analyzed that if electron trapping occurrs in the overlap region of gate and drain(G/D), it reduces GIDL current due to increment of flat-band voltage(Vfb) and if CHH is injected, interface states(Nit) were generated and it increases GIDL current due to band-to-defect-tunneling(BTDT). Especially, under dynamic stress it was confirmed that increase in GIDL current will be high when electron injection was small and CHH injection was large. Therefore as applying to real circuit, low drain voltage GIDL(BTDT) was enhaced as large as CHH Region under various operating voltage, and it will affect the reliablity of the circuit.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1564-1567
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• 2008

We demonstrate here a self-aligned printing approach that allows downscaling of printed organic thin-film transistors to channel lengths of 100 - 400 nm. A perfected down-scaled polymer transistors (L= 200 nm) showing high transition frequency over 1.5 Mhz were realized with thin polymer dielectrics, controlling contact resistance, and minimizing overlap capacitance via self-aligned gate configuration.