Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1993.07b
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- Pages.1292-1294
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- 1993
A Study on the Structure of Polycrystalline Silicon Thin Film Transistor for Reducing Off-Current
OFF 전류의 감소를 위한 다결정 실리콘 박막 트랜지스터의 구조 연구
- Oh, Jeong-Min (Dept. of Electrical Eng., Seoul Nat'l University) ;
- Min, Byung-Hyuk (Dept. of Electrical Eng., Seoul Nat'l University) ;
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Han, Min-Koo
(Dept. of Electrical Eng., Seoul Nat'l University)
- Published : 1993.07.18
Abstract
This paper proposes a new structure of polycrystalline silicon(poly-Si) thin film transistor(TFT) having a thick gate-oxide below the gate edge. The new structure is fabricated by the gate re-oxidation in wet ambient. It is shown that the thick gate-oxide below the gate edge is effective in reducing the leakage current and the gate-drain overlap capacitance. We have simulated this device by using the SSUPREM4 process simulator and the SPISCES-2B device simulator. As a simulation result it is found that the new structure provides a low tentage current less than 0.2 pA and achieves a on/off ratio as high as
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