• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.881-883
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• 2005

In case is below length 100nm of gate, various kinds problem can be happened with by threshold voltage change of device, occurrence of leakage current by tunneling because thickness of oxide by 1.5nm low scaling is done and doping concentration is increased. SiO$_2$ dielectric substance can not be used for gate insulator because is expected that tunneling current become 1A/cm$^2$ in 1.5nm thickness low. In this paper, devised double gate MOSFET(DGMOSFET) to decrease effect of leakage current by this tunneling. Therefore, could decrease effect of these leakage current in thickness 1nm low of SiO$_2$ dielectric substance. But, very big gate insulator of permittivity should be developed for develop device of nano scale.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.12
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• pp.2892-2898
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• 2015

We propose a new Double-Independent-Gate Ambipolar Silicon-Nanowire Field Effect Transistor(DIG Ambi-SiNWFET). The proposed transistor has two types of gate such as polarity gate and control gate. The polarity gate determines the operation that the gate bias controls NMOSFET or PMOSFET. The voltage of control gate controls the current characteristic of the transistor. We investigated systematically work functions of the two gates and source/drain to operate ambipolar current-voltage characteristics using 2D device simulator. When the work functions of polarity gate, control gate and source/drain are 4.75eV, 4.5eV, and 4.8eV, respectively, it showed the obvious ambipolar characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2006.05a
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• pp.865-868
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• 2006

In this paper, the subthreshold swing has been analyzed for double gate FinFET under channel length of 20nm. The analytical current model has been developed, including thermionic current and tunneling current models. The potential distribution by Poisson equation and carrier distribution by Maxwell-Boltzman statistics are used to calculate thermionic emission current, and WKB(Wentzel-Framers-Brillouin) approximation to tunneling current. The cutoff current is obtained by simple adding two currents since two current is independent. The subthreshold swings by this model are compared with those by two dimensional simulation and two values are good agreement. Since the tunneling current increases especially under channel length of 10nm, the characteristics of subthreshold swing is degraded. The channel and gate oxide thickness have to be fabricated as thin as possible to decrease this short channel effects and this process has to be developed. The subthreshold swings as a function of channel doping concentrations are obtained.

• Journal of Electrical Engineering and Technology
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• v.4 no.3
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• pp.401-404
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• 2009

A simple analytical expression for a current gain of IGBT is derived in terms of the device parameters as well as a gate length dependent parameter, which allows for the determination of the current components of the device as a function of its gate length. The analytical results are compared with those from simulation results. A good agreement is found.

• Journal of information and communication convergence engineering
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• v.7 no.1
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• pp.57-61
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• 2009

This paper has presented the subthreshold current model of FinFET using the potential variation in the doped channel based on the analytical solution of three dimensional Poisson's equation. The model has been verified by the comparison with the data from 3D numerical device simulator. The variation of subthreshold current with front and back gate bias has been studied. The variation of subthreshold swing and threshold voltage with front and back gate bias has been investigated.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.1
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• pp.48-53
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• 1994

In this paper, we present the analytical models for substrate current and gate current of stressed SC-PMOSFET using the change of the lateral electric field distribution due to the trapped electron. Calculated Isub and Ig of stressed SC-PMOSFET agree with experimental data. Our model can be very useful explaining the logarithmic time dependence of Isub and Ig. and also the trapped electron distribution.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.162-170
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• 1996

A breakdown model of gate oxides under constant current stresses is proposed. This model directly relates the oxide lifetime to the stress current density, and includes statistical nature of oxide breakdown using the concept of "effective oxide thinning". It is shown tha this model can reliably predict the TDDB characteristics for any current stress levels and oxide areas.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.64-70
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• 1995

A new DC drain-current model of GaAs MESFET with improved accuracy is proposed in this paper. The proposed model includes the decrease of current slope according to gate voltages. It is possible to represent a transconductance compression using the proposed model. It shows improved transconductance and output resistance in accuracy from the forward biased gate region to near the cutoff region. The wquaer error of saturation current is decreased by 46% compared with Statz model. The proposed model can be useful for the simulation of large-signal operation and harmonic distortion.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.7
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• pp.1-7
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• 2010

The device performances of accumulation-mode Pi-gate pMOSFETs with different fin widths have been characterized at high operating temperatures. The device fin height is 10nm and fin widths are 30nm, 40nm, and 50nm. The variation of the drain current, threshold voltage, subthreshold swing, effective mobility, and leakage current have been investigated as a function of operating temperatures. The drain current at high temperature is slightly larger than at room temperature. The variation of the threshold voltage as a function of the operating temperature is smaller than that of the inversion-mode MOSFETs. The effective mobility is decreased with the increase of operating temperature. It is observed that the effective mobility is enhanced as the fin width decreases.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.212-216
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• 1997

A new metal tip fabrication process for low voltage operation is reported in this paper. The key element of the fabrication process is that isotropic silicon etching and oxidation process used in silicon tip fabrication is utilized for gate hole size reduction and gate oxide layer. A metal FEA with 625 tips was fabricated in order to demonstrate the validity of the new process and submicron gate apertures were successfully obtained from originally 1.7$\mu\textrm{m}$ diameter mask. The emission current above noise level was observed at the gate bias of 50V. The required gate voltage to obtain the anode current of 0.1${\mu}\textrm{A}$/tip was 74V and the emission current was stable above 2${\mu}\textrm{A}$/tip without any disruption. The local field conversion factor and the emitting area were calculated as 7.981${\times}$10\ulcornercm\ulcorner and 3.2${\times}$10\ulcorner$\textrm{cm}^2$/tip, respectively.