1 |
D. Sacchetto, V. Savu, G. D. Micheli, J. Brugger, and Y. Leblebici, "Ambipolar silicon nanowire FETs with stenciled-deposited metal gate," Microelectron Eng., vol. 88, pp. 2732-2735, 2011.
DOI
|
2 |
M. De Marchi, D. Sacchetto, S. Frache, J. Zhang, P.-E. Gaillardon, Y. Leblebici, and G. De Micheli, "Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs," in Proc. IEEE IEDM, Dec. 2012, pp. 183-186.
|
3 |
J. L. Padilla, L. Knoll, F. Gamiz, Q. T. Zhao, A. Godoy, and S. Mantl, "Simulation of Fabricated 20-nm Schottky Barrier MOSFETs on SOI: Impact of Barrier Lowering", IEEE Trans. Electron Devices, vol. 59, no. 5, pp. 1320-1327, 2012.
DOI
|
4 |
ATLAS User's Manual Device Simulation Software, SILVACO, Inc., Santa Clara, CA, Nov 10, 2014.
|
5 |
K. Matsuzawa, K. Uchida, and A. Nishiyama, "A Unified Simulation of Schottky and Ohmic Contacts" IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 103-108, 2000.
DOI
|
6 |
G. E. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, no. 8, pp. 114-117, Apr. 1965.
|
7 |
M. Balaguer, B. Iniguez, and J.B. Roldan, "An analytical compact model for Schottky-barrier double gate MOSFETs", Solid-State Electronics, vol. 64, pp. 78-84, 2011.
DOI
|
8 |
D. Sacchetto, Y. Leblebici, and G. D. Micheli, "Ambipolar gate-controllable SiNW FETs for configurable logic circuits with improved expressive capability," IEEE Electron Device Lett., vol. 33, no. 2, pp. 143-145, 2012.
DOI
|
9 |
R. A. Vega, and T.-J. K. Liu, "A Comparative Study of Dopant-Segregated Schottky and Raised Source/Drain Double-Gate MOSFETs", IEEE Trans. Electron Devices, vol. 55, no. 10, pp. 2665-2677, Oct. 2008.
DOI
|
10 |
M. Schwarz, T. Holtij, A. Kloes, and B. Iniguez, "2D analytical calculation of the electric field in lightly doped Schottky barrier double-gate MOSFETs and estimation of the tunneling/thermionic current", Solid-State Electronics, vol. 63, pp.119-129, 2011.
DOI
|
11 |
H. A. Vladimirescu, A. Amara, and C. Anghel, "An analysis on the ambipolar current in Si double-gate tunnel FETs", Solid-State Electronics, vol. 70, pp. 67-72, 2012.
DOI
|
12 |
M. Schwarz, T. Holtij, A. Kloes, and B. Iniguez, "Performance study of a Schottky barrier double-gate MOSFET using a two-dimensional analytical model", IEEE Trans. Electron Devices, vol. 60, no. 2, pp. 884-886, Feb. 2013.
DOI
|
13 |
G. Zhu, X. Zhou, Y.-K. Chin, K. L. Pey, J. Zhang, G. H. See, S. Lin, Y. Yan, and Z. Chen, "Subcircuit compact model for dopant-segregated Schottky gate-all-around Si-Nanowire MOSFETs", IEEE Trans. Electron Devices, vol. 57, no. 4, pp. 772-781, Apr. 2010.
DOI
|
14 |
G. Zhu, X. Zhou, T. S. Lee, L. K. Ang, G. H. See, S. Lin, Y.-K. Chin, and K. L. Pey, "A Compact Model for Undoped Silicon-Nanowire MOSFETs With Schottky- Barrier Source/Drain", IEEE Trans. Electron Devices, vol. 56, no. 5, pp. 1100-1109, May 2009.
DOI
|