• 대한전자공학회논문지SD
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• 제41권2호
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• pp.9-15
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• 2004

본 논문에서는 부분공핍(partially-depleted : PD) 영역과 완전공핍(fully-depleted : FD) 영역을 나누는 임계 전면 게이트 전압 V/sub c/의 해석적 표현을 이용해서 PD 영역과 FD 영역의 천이를 정확히 설명하는 해석적 표면전위 모델(analytical surface potential model)을 소개한다. 이 모델은 모든 동작영역(subthreshold에서 strong inversion까지)에서 유효하고 반복 계산 절차 (iteration procedure)인 수치 해석적 방법보다 훨씬 짧은 계산시간이 걸린다. 이 모델에 기초한 charge sheet 모델이 모는 동작영역에 유효한 드레인 전류의 단일 공식을 유도하는데 사용된다. 대부분의 secondary 효과들이 charge sheet 모델에 쉽게 포함되고 그 모델의 결과들은 수치해석 결과와 실험 결과를 비교적 정확히 일치한다. 세 가지의 smoothing 함수가 사용될지 라도 표면전위 미분 값은 연속이다 더욱 중요한 점은 smoothing 함수에 사용된 파라미터들은 공정 파라미터들에 크게 의존하지 않는다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권3호
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• pp.274-283
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• 2014

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved $f_tBV_{CEO}$ product (397 GHzV). As the $BV_{CEO}$ value is higher for low value of epi layer doping, higher supply voltage can be used to increase the $f_t$ value of the HBT. At 1.8 V $V_{CE}$, the $f_tBV_{CEO}$ product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV $f_tBV_{CEO}$ product at 1.2 V $V_{CE}$). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.110-119
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• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.111-120
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• 2011

A two-dimensional analytical model for deriving the threshold voltage of a short channel fully depleted (FD) cylindrical/surrounding gate MOSFET (CGT/SGT) is suggested. By taking into account the lateral variation of the surface potential, introducing the natural length expression, and using the Bessel functions of the first and the second kinds of order zero, we can derive potentials in the gate oxide layer and the silicon core fully two-dimensionally. Making use of these potentials, the minimum surface potential can be obtained to derive the threshold voltage as a closed-form expression in terms of various device parameters and applied voltages. Obtained results can be used to explain the drain-induced threshold voltage roll-off of a CGT/SGT in a unified manner.

• 한국광학회:학술대회논문집
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• 한국광학회 1996년도 Advance Program of 13th optics andquantum Electronics conference, 1996제13 회 광학 및 양자전자 학술 발표회 논문 요약집
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• pp.10-10
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• 1996

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.473-481
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• 2012

For a mesa-isolated small geometry SOI MOSFET, the potentials in the silicon film, front, back, and side-wall oxide layers can be derived three-dimensionally. Using Taylor's series expansions of the trigonometric functions, the derived potentials are written in terms of the natural length that can be determined by using the derived formula. From the derived 3-D potentials, the minimum values of the front and the back surface potentials are derived and used to obtain the closed-form expressions for the front and back gate threshold voltages as functions of various device parameters and applied bias voltages. Obtained results can be found to explain the drain-induced threshold voltage roll-off and the narrow width effect of a fully depleted small geometry SOI MOSFET in a unified manner.

• 반도체디스플레이기술학회지
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• 제3권4호
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• pp.29-32
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• 2004

Fully depleted Silicon-on-Insulator (FD-SOI) devices lead to better electrical characteristics than bulk CMOS devices. However, the presence of a thin top silicon layer and a buried SiO2 layer causes self-heating due to the low thermal conductivity of the buried oxide. The electrical characteristics of FDSOI devices strongly depend on the path of heat dissipation. In this paper, we present a new three-dimensional (3-D) analysis technique for the self-heating effect of the finger-type and bar-type transistors. The 3-D analysis results show that the drain current of the finger-type transistor is 14.7% smaller than that of the bar-type transistor due to the 3-D self-heating effect. We have learned that the rate of current degradation increases significantly when the width of a transistor is smaller that a critical value in a finger-type layout. The current degradation fro the 3-D structures of the finger-type and bar-type transistors is investigated and the design issues are also discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권3호
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• pp.187-194
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• 2005

An analysis of the 1/f or flicker noise in FD n-channel Double Gate SOI MOSFET is proposed. In this paper, the variation of power spectral density (PSD) of the equivalent noise voltage and noise current with respect to frequency, channel length and gate-to-source voltage at various temperatures and exponent $C(i.e\;1/f^c$ is reported. The temperature is varied 125 K from to room temperature. The variation of PSD with respect to channel length down to $0.1{\mu}m$ technology is considered. It is analyzed that l/f noise in FD n-channel Double Gate SOI MOSFET is due to both carrierdensity fluctuations and mobility-fluctuations. But controversy still exits to its origin.

• 한국광학회:학술대회논문집
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• 한국광학회 2003년도 하계학술발표회
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• pp.220-221
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• 2003

We optimized the structure of a fully depleted optical thyristor (DOT) to achieve the faster switching speed and the lower power consumption by the depletion of charge at the lower negative voltage. The fabricated optical thyristor shows sufficient nonlinear s-shape I-V characteristics with the switching voltage of 2.85 V and the complete depletion voltage of -8.73 V. In this paper, using a finite difference method (FDM), we calculate the effects of parameters such as doping concentration and thickness of each layer to determine the optimized structure in the view of the fast and low-power-consuming operation.

• 대한전자공학회논문지SD
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• 제40권10호
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• pp.24-31
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• 2003

Super-steep retrograded channel (SSR)을 갖는 bulk MOSFET, fully-depleted SOI, double-gate MOSFET 구조에 대하여 단채널 효과를 비교 분석하였다. Evanescent-mode를 이용하여, 각 소자 구조에 대한 characteristics scaling-length (λ)를 추출할 수 있는 수식을 유도하고 추출된 λ의 정확도를 소자 시뮬레이션 결과와 비교하여 검증하였다. 70 nm CMOS 기술에 사용 가능하도록 단채널 효과를 효과적으로 제어하기 위해서는 최소 게이트 길이가 5λ 이상이어야 하며 SSR 소자의 공핍층 두께는 약 30 nm 정도로 스케일링되어야 한다. High-κ 절연막은 equivalent SiO2 두께를 매우 작게 유지하지 않을 경우 절연막을 통한 드레인 전계의 침투 때문에 소자를 스케일링하는데 제한을 갖는다.