JSTS:Journal of Semiconductor Technology and Science

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Epilayer Optimization of NPN SiGe HBT with n+ Buried Layer Compatible With Fully Depleted SOI CMOS Technology

  • Misra, Prasanna Kumar (Department of Electrical Engineering at IIT Kanpur) ;
  • Qureshi, S. (Department of Electrical Engineering at IIT Kanpur)
  • Received : 2014.02.20
  • Accepted : 2014.05.21
  • Published : 2014.06.30
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Abstract

In this paper, the epi layer of npn SOI HBT with n+ buried layer has been studied through Sentaurus process and device simulator. The doping value of the deposited epi layer has been varied for the npn HBT to achieve improved $f_tBV_{CEO}$ product (397 GHzV). As the $BV_{CEO}$ value is higher for low value of epi layer doping, higher supply voltage can be used to increase the $f_t$ value of the HBT. At 1.8 V $V_{CE}$, the $f_tBV_{CEO}$ product of HBT is 465.5 GHzV. Further, the film thickness of the epi layer of the SOI HBT has been scaled for better performance (426.8 GHzV $f_tBV_{CEO}$ product at 1.2 V $V_{CE}$). The addition of this HBT module to fully depleted SOI CMOS technology would provide better solution for realizing wireless circuits and systems for 60 GHz short range communication and 77 GHz automotive radar applications. This SOI HBT together with SOI CMOS has potential for future high performance SOI BiCMOS technology.

Keywords

References

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