• 한국전기전자재료학회논문지
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• 제25권4호
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• pp.247-252
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• 2012

IGBT (insulated gate bipolar transistor) has been widely used around the power industry as it has good switching performance and its excellent conductance. In order to reduce power loss during switch turn-on state, it is essential to reduce its resistance. However, trade off relationship between breakdown voltage and device conductance is the greatest obstacle on the way of improvement. Floating island structure is one of the solutions. Still, under optimized device condition for the best performance, improvement rate is negligible. Therefore, this paper suggests adding trench gate on floating island structure to eliminate JFET (junction field effect transistor) area to reduce resistance and activate floating island effect. Experimental result by 2D simulation using TCAD, shows 20% improvement of turn-on state voltage drop.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 디스플레이 광소자 분야
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• pp.187-190
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• 2000

We fabricated general photo diode, surface etched photo diode and floating gate MOSFET by CMOS process. In a design stage, we expect that surface etched photo diode will be improved as to photo sensitivity. However, because the surface of silicon was damaged in etching process, the surface etched diode had a high dark current as well as low photo current level. Finally, we examined the current-voltage properties for the floating gate MOSFET on n-well and confirmed that the device can be act as an efficient photo-sensor. The floating gate MOSFET was operated in parasitic bipolar transistor mode.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 추계학술대회
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• pp.3-4
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• 2011

This paper presents a survey of floating power supply based on bootstrap operation for three-level voltage-source inverters. The floating power supply for upper switches is achieved by the bootstrap capacitor charged during on-time of the switch underneath. Hence, a large number of bulky isolated DC/DC power supplies for each gate driver are reduced. The Pspice simulation results show the behavior of bootstrap devices and the performance of bootstrap capacitor voltage.

• 전력전자학회논문지
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• 제11권2호
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• pp.120-126
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• 2006

본 논문에서는 Multi-level PDP 구동회로의 Sustain 스위치를 구동하기 위해 Boot-strap chain 방식의 Gate driver를 제안한다. 제안된 Gate driver는 한 개의 High-side N-MOSFETS를 구동하기 위해 별도의 Floating power supply 가 필요치 않고 한 쌍의 다이오드와 캐패시터만을 사용한다. 제안 Gate driver 회로를 적용함으로서, Multi-level PDP driver의 가격과 무게 및 부피를 줄일 수 있다.

• Transactions on Electrical and Electronic Materials
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• 제7권2호
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• pp.53-57
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• 2006

In this paper, a Symmetric Dual-gate Single-Si TFT, which includes three split floating n+ zones, is simulated. This structure drastically reduces the kink-effect and improves the on-current. This is due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by a floating n+ region. This structure allows effective reduction in the kink-effect, depending on thy length of the two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA, while that of the conventional dual-gate structure is 0.5 mA, at both 12 V drain and 7 V gate voltages. This result shows an 80% enhancement in on-current. In addition, the reduction of electric field in the channel region compared to a conventional single-gate TFT and the reduction of the output conductance in the saturation region, is observed. In addition, the reduction in hole concentration, in the channel region, in order for effectively reducing the kink-effect, is also confirmed.

• 한국전기전자재료학회논문지
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• 제29권9호
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• pp.523-526
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• 2016

This paper was researched about 1,200 V level floating island IGBT (insulated gate bipolar transistor). Presently, 1,200 V level IGBT is used in Inverter for distributed power generation. We analyzed and compared electrical charateristics of the proposed floating island IGBT and conventional IGBT. For analyzing and comparison, we used T-CAD tool and simulated the electrical charateristics of the devices. And we extracted optimal design and process parameter of the devices. As a result of experiments, we obtained 1,456 V and 1,459 V of breakdown voltages, respectively. And we obatined 4.06 V and 4.09 V of threshold voltages, respectively. On the other hand, on-state voltage drop of floating island IGBT was 3.75 V. but on-state vlotage drop of the conventional IGBT was 4.65 V. Therefore, we almost knew that the proposed floating island IGBT was superior than the conventional IGBT in terms of power dissipation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.67-68
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• 2006

Floating gate non-volatile memory devices with Au nano-particles embedded in SiON or $SiO_2$ dielectrics were fabricated by digital sputtering method. The size and the density of Au are 4nm and $2{\times}10^{-12}cm^{-2}$, respectively. The floating gate memory of MOSFET with 5nm tunnel oxide and 45nm control oxide have been fabricated. This devices revealed a memory effect which due to proGrainming and erasing works perform by a gate bias stress repeatedly.

• 한국정보통신학회논문지
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• 제20권9호
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• pp.1771-1777
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• 2016

본 논문에서는 나노와이어 N-채널 GAA MOSFET의 항복전압 특성을 측정과 3 차원 소자 시뮬레이션을 통하여 분석하였다. 측정에 사용된 나노와이어 GAA MOSFET는 게이트 길이가 250nm이며 게이트 절연층 두께는 6nm이며 채널 폭은 400nm부터 3.2um이다. 측정 결과로부터 나노와이어 GAA MOSFET의 항복전압은 게이트 전압에 따라 감소하다가 높은 게이트 전압에서는 증가하였다. 나노와이어의 채널 폭이 증가할수록 항복전압이 감소한 것은 floating body 현상으로 채널의 포텐셜이 증가하여 기생 바이폴라 트랜지스터의 전류 이득이 증가한 것으로 사료된다. 게이트 스트레스로 게이트 절연층에 양의 전하가 포획되면 채널 포텐셜이 증가하여 항복전압이 감소하고 음의 전하가 포획되면 포텐셜이 감소하여 항복전압이 증가하는 것을 알 수 있었다. 항복전압의 측정결과는 소자 시뮬레이션의 포텐셜 분포와 일치하는 것을 알 수 있었다.

• 전기전자학회논문지
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• 제25권1호
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• pp.15-24
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• 2021

본 논문에서는 CDT(Conventional Double Trench) MOSFET보다 스위칭 시간과 손실이 적은 1700 V EPDT(Extended P+ shielding floating gate Double Trench) MOSFET 구조를 제안하였다. 제안한 EPDT MOSFET 구조는 CDT MOSFET에서 소스 Trench의 P+ shielding 영역을 늘리고 게이트를 N+와 플로팅 P- 폴리실리콘 게이트로 나누었다. Sentaurus TCAD 시뮬레이션을 통해 두 구조를 비교한 결과 온 저항은 거의 차이가 없었으나 Crss(게이트-드레인 간 커패시턴스)는 게이트에 0 V 인가 시에는 CDT MOSFET 대비 32.54 % 줄었고 7 V 인가 시에는 65.5 % 감소하였다. 결과적으로 스위칭 시간 및 손실은 각각 45 %, 32.6 % 줄어 스위칭 특성이 크게 개선되었다.

• 전기전자학회논문지
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• 제11권4호
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• pp.247-251
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• 2007

The recessed gate IGBT has a lower on-state voltage drop compared with the DMOS IGBT, because there is no JFET resistance. But because of the electric field concentration in the corner of the gate edge, the breakdown voltage decreases. This paper is about the new structure to effectively improve the Vce(sat) voltage without breakdown voltage drop in 1700V NPT type recessed gate IGBT with p floating shielding layer. For the fabrication of the recessed gate IGBT with p floating shielding layer, it is necessary to perform the only one implant step for the shielding layer. Analysis on the Breakdown voltage shows the improved values compared to the conventional recessed gate IGBT structures. The result shows the improvement on Breakdown voltage without worsening other characteristics of the device. The electrical characteristics were studied by MEDICI simulation results.