Electrical Characteristics of Single-silicon TFT Structure with Symmetric Dual-gate for Kink Effect Suppression |
Kang Ey-Goo
(School of Information and Communication, Far East University)
Lee Dae-Yeon (Department of Electrical Engineering, Korea University) Lee Chang-Hun (Department of Electrical Engineering, Korea University) Kim Chang-Hun (Department of Electrical Engineering, Korea University) Sung Man-Young (Department of Electrical Engineering, Korea University) |
1 | Jang, J. H., 'Novel 3-dimensional 46 SRAM technology with 0.294 (Stacked single-crystal Si) cell and SSTFT(stacked single-crystal thin film transistor)', ESSDERC, p. 21, 2004 |
2 | H. Kato, 'Consideration of poly-si loaded cell capacity limits for low power and high-speed SRAMs', IEEE JSCC, p. 683, 1992 |
3 | T. Ohzone, 'Ion-implanted Ti poly crystalline-silicon high value resistor for high density poly load static RAM application', IEEE Trans. ED. Vol. 32, p. 1749, 1985 DOI ScienceOn |
4 | J. H. Friedrich, 'A coincident-select MOS storage array', IEEE JSCC, p. 280, 1968 |
5 | Y. Tarui, 'A 40 ns 144 bit n-channel MOS LSI memory', IEEE JSCC, p. 271, 1969 |
6 | R. M. Jecmen, 'HMOS II Static RAMs overtake bipolar competition', Electronics, Vol. 52, p. 124, 1979 |