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http://dx.doi.org/10.4313/TEEM.2006.7.2.053

Electrical Characteristics of Single-silicon TFT Structure with Symmetric Dual-gate for Kink Effect Suppression  

Kang Ey-Goo (School of Information and Communication, Far East University)
Lee Dae-Yeon (Department of Electrical Engineering, Korea University)
Lee Chang-Hun (Department of Electrical Engineering, Korea University)
Kim Chang-Hun (Department of Electrical Engineering, Korea University)
Sung Man-Young (Department of Electrical Engineering, Korea University)
Publication Information
Transactions on Electrical and Electronic Materials / v.7, no.2, 2006 , pp. 53-57 More about this Journal
Abstract
In this paper, a Symmetric Dual-gate Single-Si TFT, which includes three split floating n+ zones, is simulated. This structure drastically reduces the kink-effect and improves the on-current. This is due to the separated floating n+ zones, the transistor channel region is split into four zones with different lengths defined by a floating n+ region. This structure allows effective reduction in the kink-effect, depending on thy length of the two sub-channels. The on-current of the proposed dual-gate structure is 0.9 mA, while that of the conventional dual-gate structure is 0.5 mA, at both 12 V drain and 7 V gate voltages. This result shows an 80% enhancement in on-current. In addition, the reduction of electric field in the channel region compared to a conventional single-gate TFT and the reduction of the output conductance in the saturation region, is observed. In addition, the reduction in hole concentration, in the channel region, in order for effectively reducing the kink-effect, is also confirmed.
Keywords
Single silicon TFT; Kink effect; Dual gate;
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1 Jang, J. H., 'Novel 3-dimensional 46 $F^2$ SRAM technology with 0.294 $um^2$ $S^3$(Stacked single-crystal Si) cell and SSTFT(stacked single-crystal thin film transistor)', ESSDERC, p. 21, 2004
2 H. Kato, 'Consideration of poly-si loaded cell capacity limits for low power and high-speed SRAMs', IEEE JSCC, p. 683, 1992
3 T. Ohzone, 'Ion-implanted Ti poly crystalline-silicon high value resistor for high density poly load static RAM application', IEEE Trans. ED. Vol. 32, p. 1749, 1985   DOI   ScienceOn
4 J. H. Friedrich, 'A coincident-select MOS storage array', IEEE JSCC, p. 280, 1968
5 Y. Tarui, 'A 40 ns 144 bit n-channel MOS LSI memory', IEEE JSCC, p. 271, 1969
6 R. M. Jecmen, 'HMOS II Static RAMs overtake bipolar competition', Electronics, Vol. 52, p. 124, 1979