• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.122-124
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• 2006

Ta-Mo를 co-sputtering으로 증착하여 MOS-C(Capacitor)를 제작하였다. 열적 화학적 안정성을 판별하기 위해 $600^{\circ}C$, $700^{\circ}C$, $800^{\circ}C$ 에서 급속 열처리를 행하였고, C-V 측정으로 얻은 데이터로 평탄 전압, 일함수, EOT값을 계산 하였다. I-V 측정으로 누설 전류 특성을 파악 하였다. 위의 실험 데이터를 종합하여 폴리 실리콘 게이트를 대체할 차세대 게이트 물질로써 Ta-Mo 게이트 물질을 제안하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.202-208
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• 2001

In Recent results suggested that doping $Ta_2O_5$ with a small amount of $TiO_2$ using standard ceramic processing techniques can increase the dielectric constant of $Ta_2O_5$ significantly. In this paper, this concept is studied using RTCVD (Rapid Thermal Chemical Vapor Deposition). Ti-doped $Ta_2O_5$ films are deposited using $TaC_{12}H_{30}O_5N$, $C_8H_{24}N_4Ti$, and $O_2$ on both Si and $NH_3$-nitrided Si substrates. An $NH_3$-based interface layer at the Si surface is used to prevent interfacial oxidation during the CVD process and post deposition annealing is performed in $H_2/O_2$ ambient to improve film quality and reduce leakage current. A sputtered TiN layer is used as a diffusion barrier between the Al gate electrode and the $TaTi_xO_y$ dielectric. XPS analyses confirm the formation of a ($Ta_2O_5)_{1-x}(TiO_2)_x$ composite oxide. A high quality $TaTi_xO_y$ gate stack with EOT (Equivalent Oxide Thickness) of $7{\AA}$ and leakage current $Jg=O.5A/textrm{cm}^2$ @ Vg=-1.0V has been achieved. We have also succeeded in forming a $TaTi_x/O_y$ composite oxide by rapid thermal oxidation of the as-deposited CVD TaTi films. The electrical properties and Jg-EOT characteristics of these composite oxides are remarkably similar to that of RTCVD $Ta_2O_5, suggesting that the dielectric constant of $Ta_2O_5$ is not affected by the addition of $TiO_2$.

• Journal of the Korean Vacuum Society
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• v.19 no.1
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• pp.14-21
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• 2010

Ge is one of the attractive channel materials for the next generation high speed metal oxide semiconductor field effect transistors (MOSFETs) due to its higher carrier mobility than Si. But the absence of a chemically stable thermal oxide has been the main obstacle hindering the use of Ge channels in MOS devices. Especially, the fabrication of gate oxide on Ge with high quality interface is essential requirement. In this study, $HfO_xN_y$ thin films were prepared by plasma-enhanced atomic layer deposition on Ge substrate. The nitrogen was incorporated in situ during PE-ALD by using the mixture of nitrogen and oxygen plasma as a reactant. The effects of nitrogen to oxygen gas ratio were studied focusing on the improvements on the electrical and interface properties. When the nitrogen to oxygen gas flow ratio was 1, we obtained good quality with 10% EOT reduction. Additional analysis techniques including X-ray photoemission spectroscopy and high resolution transmission electron microscopy were used for chemical and microstructural analysis.

• The Journal of the Convergence on Culture Technology
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• v.9 no.1
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• pp.663-668
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• 2023

Recently it is very important to collect information such as enemy positions and facilities. To this end, unmanned aerial vehicles such as multicopters have been actively developed, and various mission equipment mounted on unmanned aerial vehicles have also been developed. The coordinate-oriented algorithm refers to an algorithm that calculates a gaze angle so that the mission equipment can fix the gaze at a desired coordinate or position. Flight data and GPS data were collected and simulated using Matlab for coordinate-oriented algorithms. In the simulation using only the coordinate data, the average Pan axis angle was about 0.42°, the Tilt axis was 0.003°~0.43°, and the relatively wide error was about 0.15° on average. As a result of converting this into the distance in the NE direction, the error distance in the N direction was about 2.23m on average, and the error distance in the E direction was about -1.22m on average. The simulation applying the actual flight data showed a result of about 19m@CEP. Therefore, we conducted a study on the self-error of coordinate-oriented algorithms in monitoring and information collection, which is the main task of EOTS, and confirmed that the quantitative target of 500m is satisfied with 30m@CEP, and showed that the desired coordinates can be directed.

• Journal of Digital Contents Society
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• v.19 no.6
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• pp.1197-1205
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• 2018

In this paper, we perform Single Image Super Resolution(SISR) for acquired images of EOTS or IRST from naval combat system. In order to conduct super resolution, we use Generative Adversarial Networks(GANs), which consists of a generative model to create a super-resolution image from the given low-resolution image and a discriminative model to determine whether the generated super-resolution image is qualified as a high-resolution image by adjusting various learning parameters. The learning parameters consist of a crop size of input image, the depth of sub-pixel layer, and the types of training images. Regarding evaluation method, we apply not only general image quality metrics, but feature descriptor methods. As a result, a larger crop size, a deeper sub-pixel layer, and high-resolution training images yield good performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.228-239
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• 2004

In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.7
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• pp.594-599
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• 2005

In this paper, we report the properties of Mo metal employed as PMOS gate electrode. Mo on $SiO_2$ was observed to be stable up to $900^{\circ}C$ by analyzing the Interface with XRD. C-V measurement was performed on the fabricated MOS capacitor with Mo Bate on $SiO_2$. The stability of EOT and work-function was verified by comparing the C-V curves measured before and after annealing at 600, 700, 800, and $900^{\circ}C$. C-V hysteresis curve was performed to identify the effect of fired charge. Gate-injection and substrate-injection of carrier were performed to study the characteristics of $Mo-SiO_2$ and $SiO_2-Si$ interface. Sheet resistance of Mo metal gate obtained from 4-point probe was less than $10\;\Omega\Box$ that was much lower than that of polysilicon.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.23-28
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• 2004

In this paper, the properties of Mo as PMOS gate electrodes were studied. The work-function of Mo extracted from C-V characteristic curves was appropriate for PMOS. To identify the electrical and chemical stability of Mo metal gate, the changes of work-function and EOT(Effective Oxide Thickness) values were investigated after 600, 700, 800 and 90$0^{\circ}C$ RTA(Rapid Thermal Annealing). Also it was found that Mo metal gate was stable up to 90$0^{\circ}C$ with underlying SiO$_2$through X-ray diffraction measurement. Sheet resistances of Mo metal gate obtained from 4-point probe were less than 10$\Omega$/$\square$ that was much lower than those of polysilicon.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.76-82
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• 2003

The robust stack storage node and sufficient cell capacitance for high performance is indispensable for 90 nm DRAM capacitor. For the first time, we successfully demonstrated MIS capacitor process integration for 90 nm DRAM technology. Novel cell layout and integration technology of 90 nm DRAM capacitor is proposed and developed, and it can be extended to the next generation DRAM. Diamond-shaped OCS with 1.8 um stack height is newly developed for large capacitor area with better stability. Furthermore, the novel $Al_2O_3/HfO_2$ dielectric material with equivalent oxide thickness (EOT) of 25 ${\AA}$ is adopted for obtaining sufficient cell capacitance. The reliable cell capacitance and leakage current of MIS capacitor is obtained with ~26 fF/cell and < 1 fA/ceil by $Al_2O_3/HfO_2$ dielectric material, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.2
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• pp.120-124
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• 2005

In this work, MOS capacitors were used to study the electrical properties of Mo gate electrode deposited on ZrO$_2$. The workfunctions of Mo gate extracted from C-V curves were appropriate for PMOS. Thermal stability of Mo metal was investigated by analyzing the variations of workfunction and EOT(effective oxide thickness) after 600, 700, and 800 $^{\circ}C$ RTA(rapid thermal annealing). It was found that Mo gate was stable up to 800 $^{\circ}C$ with underlying ZrO$_2$. The resistivities of Mo were 35$\mu$Ω$.$cm∼ 75$\mu$Ω$.$cm. These values are lower than those of heavily doped polysilicon. Based on these measurements, it can be concluded that Mo metal gate with ZrO$_2$ gate insulator is an excellent gate material for PMOS.