• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.12
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• pp.2281-2285
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• 2011

An algorithm for extracting SPICE MOS level 2 model parameters for the high voltage MOSFET DC model is proposed. The optimization method for analyzing the nonlinear data of the current-voltage curve using the Gauss-Newton algorithm is proposed and the pre-process step for calculating the threshold voltage and the mobility is proposed. The drain current obtained from the proposed method shows the maximum relative error of 5.6% compared with the drain current of 2-dimensional device simulation for the high voltage MOSFET.

• Transactions on Electrical and Electronic Materials
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• v.17 no.5
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• pp.270-274
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• 2016

This article investigates the use of the Gaussian-channel doping profile for the control of the short-channel effects in the double-gate MOSFET whereby a two-dimensional (2D) quantum simulation was used. The simulations were completed through a self-consistent solving of the 2D Poisson equation and the Schrodinger equation within the non-equilibrium Green’s function (NEGF) formalism. The impacts of the p-type-channel Gaussian-doping profile parameters such as the peak doping concentration and the straggle parameter were studied in terms of the drain current, on-current, off-current, sub-threshold swing (SS), and drain-induced barrier lowering (DIBL). The simulation results show that the short-channel effects were improved in correspondence with incremental changes of the straggle parameter and the peak doping concentration.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1172-1175
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• 2007

We have investigated the threshold voltage shifts(${\Delta}Vth$) and drain current level shift (${\Delta}Ids$) in subthreshold region of a-Si:H TFTs induced by DC Bias (Vgs and Vds) - Temperature stress (BTS) condition. We plotted the transfer curves and the ${\Delta}Vth$ contour maps as Vds-Vds stress bias and Temperature to examine the severe damage cases on TFTs. Also, by drawing out the time-dependent transfer curve (Ids-Vgs) in the region of $10^{-8}\;{\sim}\;10^{-13}$ (A) current level, we can estimate the failure time of TFTs in a operating condition.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.635-640
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• 2016

Tunnel field-effect transistor (TFET) is a promising candidate for the next-generation electron device. However, technical issues remain for their practical application: poor current drivability, shor-tchannel effect and ambipolar behavior. We propose herein a novel recessed-channel TFET (RTFET) with the asymmetric source and drain. The specific design parameters are determined by technology computer-aided design (TCAD) simulation for high on-current and low S. The designed RTFET provides ${\sim}446{\times}$ higher on-current than a conventional planar TFET. And, its average value of the S is 63 mV/dec.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.346-346
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• 2010

A capacitorless one transistor dynamic random access memory (1T-DRAM) on silicon-germanium-on-insulator substrate was investigated. SGOI technology can make high effective mobility because of lattice mismatch between the Si channel and the SiGe buffer layer. To evaluate memory characteristics of 1T-DRAM, the floating body effect is generated by impact ionization (II) and gate induced drain leakage (GIDL) current. Compared with use of impact ionization current, the use of GIDL current leads to low power consumption and larger sense margin.

• Journal of Sensor Science and Technology
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• v.8 no.6
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• pp.434-439
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• 1999

Differential field effect transistors with double gate metal for integrated humidity sensors have been fabricated and the drain current drift characteristics to relative humidity have been investigated. The aspect ratio was 250/50 for both transistors to get the current difference between the sensing device and non-sensing one. The normalized drain current of the fabricated humidity sensitive field effect transistors increases from 0.12 to 0.3, as relative humidity increases from 30% to 90%.

• Transactions on Electrical and Electronic Materials
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• v.17 no.6
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• pp.329-334
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• 2016

In this work, the temperature dependence of electrical parameters of nanoscale SOI (silicon-on-insulator) TG (triple gate) n-FinFET (n-channel Fin field effect transistor) was investigated. Numerical device simulator $ATLAS^{TM}$ was used to construct, examine, and simulate the structure in three dimensions with different models. The drain current, transconductance, threshold voltage, subthreshold swing, leakage current, drain induced barrier lowering, and on/off current ratio were studied in various biasing configurations. The temperature dependence of the main electrical parameters of a SOI TG n-FinFET was analyzed and discussed. Increased temperature led to degraded performance of some basic parameters such as subthreshold swing, transconductance, on-current, and leakage current. These results might be useful for further development of devises to strongly down-scale the manufacturing process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.379-382
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• 2002

GaAs has wide band gap, Therefore that malarial can used high Temperature application. in this paper explain to current-voltage characteristics of thermal effect. we experiment on thermal test of current-voltage characteristics and gate leakage current with real device. As a result, we propose a current-volatage characteristics model. that model base on gate leakage current, and gate leakage current influence gate source voltage.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.713-716
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• 2013

The device performances of N-channel Tunneling FET have been characterized with different intrinsic length between drain and gate($L_{in}$), drain and source doping, permittivity and oxide thickness when the total effective channel length is constant. N-channel Tunneling FET of SOI structure have been used in characterization. $L_{in}$ was from 30nm to 70nm, dose concentration of drain and source were from $2{\times}10^{12}cm^{-2}$ to $2{\times}10^{15}cm^{-2}$ and from $1{\times}10^{14}cm^{-2}$ to $3{\times}10^{15}cm^{-2}$, permittivity was from 3.9 to 29, and oxide thickness was from 3nm to 9nm. The device performances were characterized by Subthreshold slope(S-slope), On/off ratio, and leakage current. From the simulation results, the leakage current have been reduced for long $L_{in}$ and low drain doping. S-slope have been reduced for high source doping, high permittivity and thin oxide thickness. With considering the leakage current and S-slope, it is desirable that are long $L_{in}$, low drain doping, high source doping, high permittivity and thin oxide thickness to optimize device performance in n-channel Tunneling FET.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.11
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• pp.62-69
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• 1998

The general degradation model has been applied to analyze the hot carrier induced degradation of the DC and RF characteristics of RF-nMOSFET. The degradation of cut-off frequency has been severer than the degradation of bulk MOSFET drain current. The value of the degradation rate n and the degradation parameter m for RF-nMOSFET has been equal to those for bulk MOSFET. The decrease of device degradation with the increase of fingers could be explained by the large source/drain parasitic resistance and drain saturation voltage. It has been also found that the RF performance degradation could be explained by the decrease of $g_{m}$ and $C_{gd}$ and the increase of $g_{ds}$ after stress. The degradation of the DC and RF characteristics of RF-nMOSFET could be predicted by the measurement of the substrate current.t.