• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.10a
• /
• pp.777-779
• /
• 2003

In this paper, we have investigated Characteristics of C-V for Double gate MOSFET with main gate and side gate. DG MOSFET has the main gate length of 50nm and the side gate length of 70nm. We have investigated characteristics of C-V and main gate voltage is changed from -5V to ＋5V. Also we have investigated characteristics of C-V for DG MOSFET when the side gate length is changed from 40nm to 90nm. As the side gate length is reduced, the transconductance is increased and the capacitance is reduced. When the side gate voltage is 3V, we know that C-V curves are bending at near the main gate voltage of 1.8V. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2004.05b
• /
• pp.661-663
• /
• 2004

In this paper, we have investigated characteristics of C-V for double gate MOSFET with main gate and side gate by the variation of side sate length and side gate voltage. Main gate voltage is changed from -5V to +5V. We know that characteristics of C-V is good under the condition of LSG=70nm, VSG=3V, VD=2V. We have analyze characteristics of device by ISE-TCAD.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.1
• /
• pp.163-168
• /
• 2015

This paper analyzed the deviation of tunneling current for bottom gate voltage of sub-10 nm asymmetric double gate MOSFET. The asymmetric double gate MOSFET among multi gate MOSFET developed to reduce the short channel effects has the advantage to increase the facts to be able to control the channel current, compared with symmetric double gate MOSFET. The increase of off current is, however, inescapable if aymmetric double gate MOSFET has the channel length of sub-10 nm. The influence of tunneling current was investigated in this study as the portion of tunneling current for off current was calculated. The tunneling current was obtained by the WKB(Wentzel-Kramers-Brillouin) approximation and analytical potential distribution derived from Poisson equation. As a results, the tunneling current was greatly influenced by bottom gate voltage in sub-10 nm asymmetric double gate MOSFET. Especially it showed the great deviation for channel length, top and bottom gate oxide thickness, and channel thickness.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.05a
• /
• pp.693-695
• /
• 2003

In this paper, we have investigated temperature-dependent characteristics of current-voltage for double gate MOSFET with main gate and side gate. DG MOSFET has the main gate length of 50nm and the side gate length of 70nm. We have investigated the temperature-dependent characteristics of current-voltage and drain voltage is changed from 0V to 5.0V at $V_{mg}$ =1.5V and $V_{sg}$ =3.0V. We have obtained a very good characteristics of current-voltage for 77K. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.12
• /
• pp.10-17
• /
• 2009

Nano-Electro-Mechanical MOSFET (NEMFET) using Double-Gate MOSFET (DGMOS) structure can efficiently control the short channel effect. Espatially, subthreshold current of depletion-mode Double-Gate NEMFET (Dep-DGNEMFET) decreases in the off-state due to the thin equivalent-oxide thickness. Analytical $t_gap$ vs. $V_g$ equation for Dep-DGNEMFET is derived and characteristics for different device structures are analyzed. Dep-DGNEMFET structure is optimized to satisfy ITRS criteria.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.11a
• /
• pp.490-493
• /
• 2002

In this study, we have investigated optimum value for side gate length and side gate voltage of double gate (DG) MOSFET with main gate and side gate. We know that optimum side gate voltage for each side length is about 3V. Also, we know that optimum side gate length for each main gate length is about 70nm. We have presented the transconductance and subthreshold slope for each side gate length. We have simulated using ISE-TCAD tool for characteristics analysis of device.

• Journal of IKEEE
• /
• v.25 no.1
• /
• pp.15-24
• /
• 2021

In this paper, 1700 V EPDT (Extended P+ shielding floating gate Double Trench) MOSFET structure, which has a smaller switching time and loss than CDT (Conventional Double Trench) MOSFET, is proposed. The proposed EPDT MOSFET structure extended the P+ shielding area of the source trench in the CDT MOSFET structure and divided the gate into N+ and floating P- polysilicon gate. By comparing the two structures through Sentaurus TCAD simulation, the on-resistance was almost unchanged, but Crss (Gate-Drain Capacitance) decreased by 32.54 % and 65.5 %, when 0 V and 7 V was applied to the gate respectively. Therefore, the switching time and loss were reduced by 45 %, 32.6 % respectively, which shows that switching performance was greatly improved.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.10
• /
• pp.16-24
• /
• 2009

Independent-gate-mode double-gate(IGM-DG) MOSFET overcomes the limitation of 3-terminal device structure, and enables to operate with different voltages for front-gate and back-gate. Therefore, circuit designs becomes not only simple, but also area-efficient due to the controllability of the 4th terminal provided by IGM-DG MOSFETs. In this paper, an RF receiver utilizing IGM-DG MOSFETs is presented and also, the circuit performance is verified by the HSPICE simulations. Besides, the circuit analysis and optimization are performed for various IGM-DG characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2003.05a
• /
• pp.690-692
• /
• 2003

In this paper, we have investigated characteristics of radio frequency for double gate MOSFET with 50nm main gate in according to variation of side gate length. We could know the increasement of cut-off frequency as the side gate length is lower. As a result, we could know the most optimum performance characteristics when side gate length was 70nm. In this time, the DG MOSFET of side gate with 70nm has very high cut-off frequency like 41.4GHz.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.10 no.6
• /
• pp.243-249
• /
• 2010

In this thesis, in order to a equivalent circuit-analytical study for a symmetric double gate type MOSFET, we slove analytically the 2D Poisson's equation in a a silicon body. To solve the threshold voltage in a symmetric double gate type MOSFET from the derived expression for the surface potential which the two-dimensional potential distribution of a symmetric double gate type MOSFET is assumed approximately. This thesis can use short and long channel in a silicon body we introduce a new the threshold voltage model in a symmetric double gate type MOSFET and measure it the distance about the range of channel length up to 0.1 [${\mu}m$].