대한전자공학회논문지SD (Journal of the Institute of Electronics Engineers of Korea SD)

대한전자공학회 (The Institute of Electronics and Information Engineers)
권호 표지

Double-Gate MOSFET을 이용한 공핍형 NEMFET의 특성 분석 및 최적화

Analysis and Optimization of a Depletion-Mode NEMFET Using a Double-Gate MOSFET

  • 김지현 (이화여자대학교 전자공학과) ;
  • 정나래 (이화여자대학교 전자공학과) ;
  • 김유진 (이화여자대학교 전자공학과) ;
  • 신형순 (이화여자대학교 전자공학과)
  • Kim, Ji-Hyun (Department of electronics engineering, Ewha Womans University) ;
  • Jeong, Na-Rae (Department of electronics engineering, Ewha Womans University) ;
  • Kim, Yu-Jin (Department of electronics engineering, Ewha Womans University) ;
  • Shin, Hyung-Soon (Department of electronics engineering, Ewha Womans University)
  • 발행 : 2009.12.25
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초록

Double-Gate MOSFET 구조를 사용한 Nano-Electro-Mechanical MOSFET (NEMFET)는 게이트 길이가 짧아지면서 나타나는 단채널 현상을 효과적으로 제어하는 새로운 구조의 차세대 소자이다. 특히 공핍형 Double-gate NEMFET (Dep-DGNEMFET)은 차단 상태에서 얇은 산화막을 가지므로 subthreshold 전류가 효과적으로 제어된다. 이러한 Dep-DGNEMFET 특성에 대한 해석적 수식을 유도하고 소자 구조가 변화하는 경우의 특성 변화를 분석하였다. 또한 ITRS (International Technology Roadmap for Semiconductors) 전류 기준값을 만족시키기 위하여 Dep-DGNEMFET 소자 구조를 최적화 하였다.

Nano-Electro-Mechanical MOSFET (NEMFET) using Double-Gate MOSFET (DGMOS) structure can efficiently control the short channel effect. Espatially, subthreshold current of depletion-mode Double-Gate NEMFET (Dep-DGNEMFET) decreases in the off-state due to the thin equivalent-oxide thickness. Analytical $t_gap$ vs. $V_g$ equation for Dep-DGNEMFET is derived and characteristics for different device structures are analyzed. Dep-DGNEMFET structure is optimized to satisfy ITRS criteria.

키워드

참고문헌

  1. H. Daggour and K. Banerjee, "Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications," DAC 2007, pp. 300-311, California, USA., June 2007
  2. B. Pruvost and H Mizuta, "3-D Design and Analysis of Function NEMs-gate MOSFETs and SETs," IEEE Trans. on Nanotechnology, vol. 6, no. 2, pp. 218-224, March 2007 https://doi.org/10.1109/TNANO.2007.891825
  3. A. M.Ionescu, V. Pott, R. Fritschi, K. Banerjee, M. Declercq, P. Renaud, C. Hibert, P. Fluckiger, and G. Racine, "Modeling and Design of a Low-Voltage SOl Suspended-Gate MOSFET (SG-MOSFET) with a Metal-Over Gate Architecture," in Proc. of IEEE ISQED, pp. 469-501, California, USA., March 2002
  4. H. Kam, D. Lee, R. Howe, and T. King, "A New Nano-Mechnical Field Effect Transistor (NEMFET) Design for Low-Power Electronics", IEDM Tech Digest., pp. 463-466, Washington, USA., Dec 2005
  5. M. Fernandez-Bolanos, N. Abele, V. Pott, D. Bouvet, G. Racine, J. Qcuro, and A. lonescu "Polymide sacrificial layer for SOl SG-MOSFET pressure sensor," MicroElectronic Engineering, vol. 83, no. 4, pp. 1185-1188, April 2006 https://doi.org/10.1016/j.mee.2005.12.021
  6. L. Dobrescu, D. Dobrescu, A. Rusu, and C. Ravariu, "Mechanical Influences on the Electrical characteristics of the Mobile Gate MOS Capacitors," in Proc. of IEEE MIEL, vol. 1, pp. 227-230, Nis, Yugoslavia, May 2002
  7. A. Bansal and K. Roy, "Analytical Subthreshold Potential Distribution Model for Gate Underlap Double-Gate MOS Transistors," IEEE trans. on Electron Devices, vol 54, no. 7, pp. 1793-1798, July 2007 https://doi.org/10.1109/TED.2007.898042
  8. Y. Tsividis, "Operation and Modeling of The MOS Transistor," McGraw -Hill, pp. 327-331, 1999
  9. "ATLAS User's Manual, Device Simulation Software 1-2," SIVACO International, 2006