• 한국전기전자재료학회논문지
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• 제36권4호
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• pp.385-390
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• 2023

In this paper, the 1,700 V level SiC-based power MOSFET device widely used in electric vehicles and new energy industries was designed, that is, a single trench gate power MOSFET structure and a double trench gate power MOSFET structure were proposed to analyze electrical characteristics while changing the design and process parameters. As a result of comparing and analyzing the two structures, it can be seen that the double trench gate structure shows quite excellent characteristics according to the concentration of the drift layer, and the breakdown voltage characteristics according to the depth of the drift layer also show excellent characteristics of 200 V or more. Among them, the trench gate power MOSFET device can be applied not only to the 1,700 V class but also to a voltage range above it, and it is believed that it can replace all Si devices currently applied to electric vehicles and new energy industries.

• 한국정보통신학회논문지
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• 제20권4호
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• pp.799-804
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• 2016

본 논문에서는 비대칭 이중게이트 MOSFET의 상하단 게이트 산화막 두께에 대한 드레인 유도 장벽 감소 현상을 분석하기 위하여 전위장벽에 영향을 미치는 드레인전압에 따른 문턱전압의 변화를 관찰할 것이다. 비대칭 이중게이트 MOSFET는 상단과 하단의 게이트 산화막 두께를 다르게 제작할 수 있는 특징이 있다. 상단과 하단의 게이트 산화막 두께 변화에 따른 드레인 유도 장벽 감소 현상에 대하여 포아송방정식을 이용하여 분석하였다. 결과적으로 드레인 유도 장벽 감소 현상은 상하단 게이트 산화막 두께에 따라 큰 변화를 나타냈다. 상단과 하단 게이트 산화막 두께가 작을수록 드레인 유도 장벽은 선형적으로 감소하였다. 채널길이에 대한 드레인 유도 장벽 감소 값은 비선형적인 관계가 있었다. 고농도 채널도핑의 경우 상단 산화막 두께가 하단 산화막 두께보다 드레인 유도 장벽 감소에 더 큰 영향을 미치고 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.500-510
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• 2013

In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.

• 대한전자공학회논문지SD
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• 제45권10호
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• pp.15-22
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• 2008

기존의 MOSFET는 단채널 현상의 증가로 인하여 스케일링에 한계를 가지고 있다. Double-Gate MOSFET (DG-MOSFET)는 소자의 길이가 축소되면서 나타나는 단채널 현상을 효과적으로 제어하는 차세대 소자이다. DG-MOSFET으로 소자를 축소시키면 채널 길이가 10nm 이하에서 게이트 방향뿐만 아니라 소스와 드레인 방향에서도 양자 효과가 발생한다. 또한 게이트 길이가 매우 짧아지면 ballistic transport 현상이 발생한다. 따라서 본 연구에서는 2차원 양자 효과와 ballistic transport를 고려하여 DG-MOSFET의 특성을 분석하였다. 또한 단채널 효과를 줄이기 위해서 $t_{si}$와 underlap 그리고 lateral doping gradient를 이용하여 소자 구조를 최적화하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.127-138
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• 2013

The impact of Empty Space layer in the channel region of a Double Gate (i.e. ESDG) MOSFET has been studied, by monitoring the DC, RF as well as the digital performance of the device using ATLAS 3D device simulator. The influence of temperature variation on different devices, i.e. Double Gate incorporating Empty Space (ESDG), Empty Space in Silicon (ESS), Double Gate (DG) and Bulk MOSFET has also been studied. The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of $VIP_2$ and $VIP_3$. The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.331-341
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• 2013

In the present work, the effect of the gate-to-drain capacitance ($C_{gd}$) on the noise performance of a symmetric tied-gate $In_{0.52}Al_{0.48}As/In_{0.53}Ga_{0.47}As$ double-gate HEMT is studied using an accurate charge control based approach. An analytical expression for the gate-to-drain capacitance is obtained. In terms of the intrinsic noise sources and the admittance parameters ($Y_{11}$ and $Y_{21}$ which are obtained incorporating the effect of $C_{gd}$), the various noise performance parameters including the Minimum noise figure and the Minimum Noise Temperature are evaluated. The inclusion of gate-to-drain capacitance is observed to cause significant reduction in the Minimum Noise figure and Minimum Noise Temperature especially at low values of drain voltage, thereby, predicting better noise performance for the device.

• 한국정보통신학회논문지
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• 제9권8호
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• pp.1749-1753
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• 2005

본 논문에서는 메인게이트와 사이드게이트를 갖는 더블게이트 구조의 동작 온도에 따른 전기적 특성들을 조사하였다. 실온(300K)에서 뿐만 아니라 극저온(77K)에서도 전류-전압특성이 우수함을 알 수 있었다. 또한 우수한 DG MOSFET의 동적 특성들을 얻기 위한 최적의 조건들은 메인게이트 길이가 50nm이고 사이드게이트 길이가 70nm, 그리고 드레인 전압이 2V이상 인가되어야 함을 알 수 있었다. 실온에서 문턱전압은 약0.358V, 77K에서는 약 0.513V를 얻을 수 있었다. 또한 온-오프 특성이 우수하여 디지털 소자로서 유용하게 사용될 수 있을 것이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.192-198
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• 2017

In this paper, we propose a novel double gate vertical channel tunneling field effect transistor (DVTFET) with a dielectric sidewall and optimization characteristics. The dielectric sidewall is applied to the gate region to reduced ambipolar voltage ($V_{amb}$) and double gate structure is applied to improve on-current ($I_{ON}$) and subthreshold swing (SS). We discussed the fin width ($W_S$), body doping concentration, sidewall width ($W_{side}$), drain and gate underlap distance ($X_d$), source doping distance ($X_S$) and pocket doping length ($X_P$) of DVTFET. Each of device performance is investigated with various device parameter variations. To maximize device performance, we apply the optimum values obtained in the above discussion of a optimization simulation. The optimum results are steep SS of 32.6 mV/dec, high $I_{ON}$ of $1.2{\times}10^{-3}A/{\mu}m$ and low $V_{amb}$ of -2.0 V.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.110-119
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• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• Journal of electromagnetic engineering and science
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• 제2권1호
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• pp.56-58
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• 2002

In this paper, the double conversion gate mixer using a half-LO frequency is described at 25 GHz band. The proposed mixer uses two HEMTs excited by a single LO signal of half-LO frequency in order to generate the second IF signal. That is, the LO signal having the half-LO frequency is only fed into the gate of the first HEMT mixer as a normal gate mixer. The LO signal through the first mixer is find into the second mixer The proposed miler requires not only half of the normal LO frequency, but also lower LO power than the conventional subharmonically pumped milers. Over the bandwidth of 500 MHz at 24.5 GHz, the conversion gain is 2.5 dB, the noise figure is 9 dB, and the isolation between RF and LO port is 32 dB when the LO poller is 0 dBm at 12.65 GHz.