JSTS:Journal of Semiconductor Technology and Science

  • 제13권2호
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  • Pages.127-138
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  • 2013
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Investigation of Empty Space in Nanoscale Double Gate (ESDG) MOSFET for High Speed Digital Circuit Applications

  • Kumari, Vandana (Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi) ;
  • Saxena, Manoj (Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi) ;
  • Gupta, R.S. (Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology) ;
  • Gupta, Mridula (Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi)
  • 투고 : 2012.06.14
  • 심사 : 2012.10.30
  • 발행 : 2013.04.30
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초록

The impact of Empty Space layer in the channel region of a Double Gate (i.e. ESDG) MOSFET has been studied, by monitoring the DC, RF as well as the digital performance of the device using ATLAS 3D device simulator. The influence of temperature variation on different devices, i.e. Double Gate incorporating Empty Space (ESDG), Empty Space in Silicon (ESS), Double Gate (DG) and Bulk MOSFET has also been studied. The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of $VIP_2$ and $VIP_3$. The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.

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참고문헌

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