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http://dx.doi.org/10.5573/JSTS.2013.13.2.127

Investigation of Empty Space in Nanoscale Double Gate (ESDG) MOSFET for High Speed Digital Circuit Applications  

Kumari, Vandana (Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi)
Saxena, Manoj (Department of Electronics, Deen Dayal Upadhyaya College, University of Delhi)
Gupta, R.S. (Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology)
Gupta, Mridula (Semiconductor Device Research Laboratory, Department of Electronic Science, University of Delhi)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.13, no.2, 2013 , pp. 127-138 More about this Journal
Abstract
The impact of Empty Space layer in the channel region of a Double Gate (i.e. ESDG) MOSFET has been studied, by monitoring the DC, RF as well as the digital performance of the device using ATLAS 3D device simulator. The influence of temperature variation on different devices, i.e. Double Gate incorporating Empty Space (ESDG), Empty Space in Silicon (ESS), Double Gate (DG) and Bulk MOSFET has also been studied. The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of $VIP_2$ and $VIP_3$. The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.
Keywords
ATLAS 3D; double gate; empty space in silicon; circuits;
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