• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.1
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• pp.45-48
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• 2010

An inter-pin skew compensation scheme is proposed, which minimizes the inter-pin skew of parallel interface induced by unequal trace length and loading of printed circuit board (PCB). The proposed scheme measures the inter-pin skew and compensates during power-up with simple hardware. The proposed scheme is applied to 3.2-Gb/s/pin DDR4 SDRAM and implemented in a 0.18 m CMOS process. The inter-pin skew is compensated in 324-cycles of 400-MHz clock and the skew is compensated to be less than 24-ps.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.521-527
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• 2011

POWER PC series are common to the Central Processing Unit for Military Single Board Computer. Among them, G4 group, which contains the 74xx series supported by Freescale manufacturer is mainly used in the Military applications. We focus on the Interface between memory and controller. PCB stacking method, component routing, impedance matching and harsh environment for Military spec are the main constraints for implementation. Also, we developed memory as a module for the consideration of Military environments. The overall type of SBC should be designed by the form of 6U VME or 3U VME. Therefore this study suggests the electrically optimum Interface matching, Artwork technology based on the signal cross over and PCB stacking method on the harsh environment.

• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.247-254
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• 2003

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.

• Journal of the Architectural Institute of Korea Planning & Design
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• v.36 no.2
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• pp.33-42
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• 2020

On October 3, 1990, Germany achieved peaceful reunification by integrating East Germany into West Germany. Since reunification, the region of East Germany had to have a new value standard in extreme social changes such as legal, political, administrative and spatial amid rapid systemic changes. The purpose of this study is to characterize urban policy related to urban change in DDR in the past 30 years after German unification. In particular, this study examined the change of construction law and Städtebauförderung Program as urban policy. The characteristics of Städtebauförderung programs and urban regeneration are in context with their contents. The characteristics of Städtebauförderung program support program are ultimately aimed at resolving imbalances among cities, improving the quality of life of residents and developing cities with future-oriented sustainability.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.3
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• pp.203-208
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• 2017

Recently, the importance of DRAM is very significant in multicore processors which are widely used in computers, laptops, tablet PCs, and mobile devices. To keep up with this, both industry and academia have actively studied various types of future DRAMs. Therefore, accurate DRAM model is requisite when evaluating the multicore processor performance. In this paper, a multicore processor trace-driven simulator which can couple with the cycle-accurate DRAM simulator has been developed. Using SPEC 2000 benchmarks as input, the effect of cycle-accurate DDR3 model on the multicore processor performance has been evaluated.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.1
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• pp.219-224
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• 2017

Recently, the importance of DRAM is very significant not only in embedded systems and mobile devices but also in high-end modern microprocessors and multicore processors. To keep up with this, both industry and academia have actively studied various types of future DRAMs. Therefore, accurate DRAM model is requisite when evaluating the microprocessor performance. In this paper, a microprocessor trace-driven simulator which can couple with the cycle-accurate DRAM simulator has been developed. Using SPEC 2000 benchmarks as input, the effect of cycle-accurate DDR3 model on the microprocessor performance has been evaluated.

• The Korean Journal of Food And Nutrition
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• v.33 no.3
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• pp.309-316
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• 2020

In this study, we investigated the protective effects of Ulva lactuca methanol extracts against ultraviolet B (UVB)-induced DNA damage in HaCaT cells. First, the contents of general and antioxidative nutrient contents of Ulva lactuca were measured. The moisture, carbohydrate, crude protein, crude fat and ash were 14.01%, 44.80%, 23.19%, 3.10% and 14.90%, respectively. Magnesium that acts as DNA repair enzyme cofactor was the most abundant mineral followed by Ca, P and Fe. The total phenolic and anthocyanoside contents of Ulva lactuca were 2.69 mg/g and 0.13 mg/g, respectively. Cells treated with Ulva lactuca methanol extracts for 24 hours post UVB exposure increased cell viability in a concentration-dependent manner compared to the non-treated control. Also, Ulva lactuca methanol extracts decreased the levels of UVB-induced DNA damage such as cyclobutane pyrimidine dimer and DNA damage response (DDR) proteins such as p-p53 and p21. These results suggest that Ulva lactuca methanol extracts comprising physiological active substances such as Mg, polyphenols and anthocyanosides promote DNA repair by regulating genes related with DDR.

• IE interfaces
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• v.5 no.1
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• pp.3-14
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• 1992

This paper deals with the development of setup planning for Automated FIXture planning system(AFIX) which selects setups, setup sequence and operation sequence in each setup according to the machining mode. In AFIX, part type considered is prismatic workpiece that use the 3-2-1 locating system as the general structure of the fixture. The heuristic algorithms selecting setup and setup sequence are based on DDR(Degree of Dimensional Relationship), AMV(Admissible Misalignment Value) and machining sterategy and feature attributes. A case example is given to illustrate the performance fo AFIX.

• Journal of Korea Multimedia Society
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• v.14 no.3
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• pp.368-377
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• 2011

This paper explains the hardware structure of SURF(Speeded Up Robust Feature) based feature point extractor and its FPGA verification result. SURF algorithm produces novel scale- and rotation-invariant feature point and descriptor which can be used for object recognition, creation of panorama image, 3D Image restoration. But the feature point extraction processing takes approximately 7,200msec for VGA-resolution in embedded environment using ARM11(667Mhz) processor and 128Mbytes DDR memory, hence its real-time operation is not guaranteed. We analyzed integral image memory access pattern which is a key component of SURF algorithm to reduce memory access and memory usage to operate in c real-time. We assure feature extraction that using a Vertex-5 FPGA gives 60frame/sec of VGA image at 100Mhz.