JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Inter-Pin Skew Compensation Scheme for 3.2-Gb/s/pin Parallel Interface

  • Lee, Jang-Woo (Division of Electrical & Computer Engineering, Hanyang University) ;
  • Kim, Hong-Jung (Division of Electrical & Computer Engineering, Hanyang University) ;
  • Nam, Young-Jin (Division of Electrical & Computer Engineering, Hanyang University) ;
  • Yoo, Chang-Sik (Division of Electrical & Computer Engineering, Hanyang University)
  • Received : 2009.10.01
  • Published : 2010.03.31
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Abstract

An inter-pin skew compensation scheme is proposed, which minimizes the inter-pin skew of parallel interface induced by unequal trace length and loading of printed circuit board (PCB). The proposed scheme measures the inter-pin skew and compensates during power-up with simple hardware. The proposed scheme is applied to 3.2-Gb/s/pin DDR4 SDRAM and implemented in a 0.18 m CMOS process. The inter-pin skew is compensated in 324-cycles of 400-MHz clock and the skew is compensated to be less than 24-ps.

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References

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