1 |
J. Lee, "A Study of Trace-driven Simulation for Multi-core Processor Architectures," Journal of The Institute of Internet, Broadcasting and Communication, vol. 12, no. 3, pp. 9-13, Jun. 2012.
DOI
|
2 |
T. Austin, E. Larson, and D. Ernest, "SimpleScalar : An Infrastructure for Computer System Modeling," Computer, Vol. 35, No. 2, pp. 59-67, Feb. 2002.
DOI
|
3 |
JEDEC, JESD79-3 DDR3 SDRAM Standard, June 2007.
|
4 |
P. Rosenfeld et al. "DRAMSim2: A Cycle Accurate Memory System Simulator," IEEE Computer Architecture Letters, 2011.
|
5 |
Y. Kim et al. "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM," ISCA, 2012.
|
6 |
D. Lee et al. "Tiered-Latency DRAM : A Low Latency and Low Cost DRAM Architecture," HPCA, 2013.
|
7 |
Y. Kim, W. Yang, and O. Mutlu, "Ramulator : A Fast and Extensible DRAM Simulator," IEEE Computer Architecture Letters, 2015.
|