Browse > Article
http://dx.doi.org/10.7236/JIIBC.2017.17.3.203

The DRAM Effects on The Performance of Multicore Processors  

Lee, Jongbok (Dept. of Electronic & Information Eng., Hansung University)
Publication Information
The Journal of the Institute of Internet, Broadcasting and Communication / v.17, no.3, 2017 , pp. 203-208 More about this Journal
Abstract
Recently, the importance of DRAM is very significant in multicore processors which are widely used in computers, laptops, tablet PCs, and mobile devices. To keep up with this, both industry and academia have actively studied various types of future DRAMs. Therefore, accurate DRAM model is requisite when evaluating the multicore processor performance. In this paper, a multicore processor trace-driven simulator which can couple with the cycle-accurate DRAM simulator has been developed. Using SPEC 2000 benchmarks as input, the effect of cycle-accurate DDR3 model on the multicore processor performance has been evaluated.
Keywords
DRAM; DDR3; multicore processor;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 J. Lee, "A Study of Trace-driven Simulation for Multi-core Processor Architectures," Journal of The Institute of Internet, Broadcasting and Communication, vol. 12, no. 3, pp. 9-13, Jun. 2012.   DOI
2 T. Austin, E. Larson, and D. Ernest, "SimpleScalar : An Infrastructure for Computer System Modeling," Computer, Vol. 35, No. 2, pp. 59-67, Feb. 2002.   DOI
3 JEDEC, JESD79-3 DDR3 SDRAM Standard, June 2007.
4 P. Rosenfeld et al. "DRAMSim2: A Cycle Accurate Memory System Simulator," IEEE Computer Architecture Letters, 2011.
5 Y. Kim et al. "A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM," ISCA, 2012.
6 D. Lee et al. "Tiered-Latency DRAM : A Low Latency and Low Cost DRAM Architecture," HPCA, 2013.
7 Y. Kim, W. Yang, and O. Mutlu, "Ramulator : A Fast and Extensible DRAM Simulator," IEEE Computer Architecture Letters, 2015.