Browse > Article
http://dx.doi.org/10.3745/KIPSTA.2003.10A.3.247

Design of Low Voltage 1.8V, Wide Range 50∼500MHz Delay Locked Loop for DDR SDRAM  

Koo, In-Jae (하이닉스 반도체 System-IC SoC설계팀)
Chung, Kang-Min (성균관대학교 전기전자컴퓨터공학부)
Publication Information
The KIPS Transactions:PartA / v.10A, no.3, 2003 , pp. 247-254 More about this Journal
Abstract
This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.
Keywords
DLL;
Citations & Related Records
연도 인용수 순위
  • Reference
1 David J. Foley et al., 'COMS DLL-Based 2-V 3.2-ps Jitter 1GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator,' IEEE Journal of solid-State Circuits, Vol.36, Mar., 2001   DOI   ScienceOn
2 Jae Joon Kim et al., 'A low-jitter mixed-mode DLL for high-speed DRAM applications,' IEEE Journal of solid-State Circuits, Vol.35, Oct., 2000   DOI   ScienceOn
3 Sung Sik Hwang, 'Daul-loop DLL-based clock synchronizer,' Electronics Letters, Vol.36, July, 2000
4 Guang-Kaai Dehng et al., 'Clock-deskew buffer using a SAR-controlled delay-locked loop,' IEEE Journal of solid-State Circuits, Vol.35, Aug., 2000   DOI   ScienceOn
5 Yongsam Moon et al., 'An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance,' IEEE Journal of solid-State Circuits, Vol.35, Mar., 2000   DOI   ScienceOn
6 Foley D.J. et al., 'A 3.3V, 1.6GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5/spl mu/m CMOS,' The 2000 IEEE International Symposium on ISCAS 2000 Geneva Proceedings Circuits and Systems, Vol.2, 2000   DOI
7 Hamamoto T. et al., 'A skew and jitter suppressed DLL architecture for high frequency DDR SDRAMs,' Symposium on Digest of Technical Papers VLSI Circuits, 2000   DOI
8 Mota M. et al., 'A high-resoultion time interpolator based on a delay locked loop and an RC delay line,' IEEE Journal of solid-State Circuits, Vol.34, Oct., 1999
9 Kuge, S. et al., 'A 0.18-/spl mu/m 256-mb DDR-SRAM with low-cost post-mold tuning method for DLL replica,' IEEE Journal of solid-State Circuits, Vol.35, Nov., 2000   DOI   ScienceOn
10 Yongsam Moon et al., 'A 1Gbps transceiver with receiverend deskewing capability using non-uniform tracked over-sampling and a 250 - 750MHz four-phase DLL,' Symposium on Digest of Technical Papers VLSI Circuits, 1999
11 Nagavarapu S. et al., 'An asynchronus data recovery/retransmission technique with foreground DLL calibration,' ISCAS '99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, Vol.6, 1999   DOI
12 Dudek P. et al., 'A high-resoultion CMOS time-to-digital converter utilizing a Vernier delay line,' IEEE Journal of solid-State Circuits, Vol.35, Feb., 2000   DOI   ScienceOn
13 Se-Jun Kim, 'A 34MHz-400MHz Skew Calibrated DLL with Programmable Replica Delay and Dual Loop Architecture,' The 8th Korean Conference on Simiconductors, pp.479-480, Feb., 2000
14 Sung-Sik Hwang, 'A DLL based 10-320MHz clock synchronizer,' The 2000 IEEE International Symposium on ISCAS 2000 Geneva Proceedings Circuits and Systems, Vol.5, 2000   DOI
15 Yongsam Moon et al., 'A 62.5MHz-250MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cells,' Proceedings of the IEEE 1999 Custom Integrated Circuits, 1999
16 Garlepp B.W. et al., 'A portable digital DLL for high-speed CMOS interface circuits,' IEEE Journal of solid-State Circuits, Vol.34, May, 1999   DOI   ScienceOn
17 Feng Lin et al., 'A register-controlled symmetrical DLL for double-data-rate DRAM,' IEEE Journal of solid-State Circuits, Vol.34, Apr., 1999   DOI   ScienceOn
18 Portmann C. et al., 'A multiple vendor 2.5-V DLL for 1.6-GB/s RDRAMs,' Symposium on Digest of Technical Papers VLSI Circuits, 1999   DOI