• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.321-334
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• 2003

Globally-Asynchronous Locally-Synchronous (GALS) systems are worthy of notice as an adequate architecture for a large scaled chip design with guaranteeing easy designs and functional confidence. In this paper, we suggest an advanced structure of the interface unit which is indispensable for GALS systems by using stoppable clocks. The proposed interface unit is composed of a sender module and a receiver module. The sender module can carry out data transmission partially without the relation to an internal clock. We have designed it with 0.25${\mu}{\textrm}{m}$ standard cell library at the gate level and simulated its operation to show performance improvement. Finally, we constructed all example circuit with the interface unit and proved the correct operation of it.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.395-404
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• 2016

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

• Journal of Communications and Networks
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• v.13 no.1
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• pp.1-5
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• 2011

Feedback with carry shift registers (FCSRs) over 2-adic number would be suitable in hardware implementation, but the are not efficient in software implementation since their basic unit (the size of register clls) is 1-bit. In order to improve the efficiency we consider FCSRs over $2^{\ell}$-adic number (i.e., FCSRs with register cells of size ${\ell}$-bit) that produce ${\ell}$ bits at every clocking where ${\ell}$ will be taken as the size of normal words in modern CPUs (e.g., ${\ell}$ = 32). But, it is difficult to deal with the carry that happens when the size of summation results exceeds that of normal words. We may use long variables (declared with 'unsigned _int64' or 'unsigned long long') or conditional operators (such as 'if' statement) to handle the carry, but both the arithmetic operators over long variables and the conditional operators are not efficient comparing with simple arithmetic operators (such as shifts, maskings, xors, modular additions, etc.) over variables of size ${\ell}$-hit. In this paper, we propose some conditions for FCSRs over $2^{\ell}$-adic number which admit fast software implementations using only simple operators. Moreover, we give two implementation examples for the FCSRs. Our simulation result shows that the proposed methods are twice more efficient than usual methods using conditional operators.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.25-32
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• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a 0.18-${\mu}m$ 1-poly 6-metal CMOS with a 1.8 V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gb/s. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.68-75
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• 2009

In this paper, an efficient proposed CDR(Clock and Data Recovery Circuits) using 1/4-rate clock based on dual-interpolator is proposed. The CDR is aimed to overcome problems that using multi-phase clock to decrease the clock generator frequency causes side effects such as the increased power dissipation and hardware complexity, especially when the number of channels is high. To solve these problems, each recovery part generates needed additional clocks using only inverters, but not flip-flops while maintaining the number of clocks supplied from a clock generator the same as 1/2-rate clock method. Thus, the reduction of a clock generator frequency using 1/4-rate clocking helps relax the speed limitation and power dissipation when higher data rate transfer is demanded.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.3
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• pp.44-54
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• 2000

In this paper, a design methodology for the frequency-adaptive negative-delay circuit which can be implemented in standard CMOS memory process is proposed. The proposed negative-delay circuit which is a basic type of the analog SMD (synchronous mirror delay) measures the time difference between the input clock period and the target negative delay by utilizing analog behavior and repeats it in the next coming cycle. A new technology that compensates the auxiliary delay related with the output clock in the measure stage differentiates the Proposed method from the conventional method that compensates it in the delay-model stage which comes before the measure stage. A wider negative-delay range especially prominent in the high frequency performance than that in the conventional method can be realized through the proposed technology. In order to implement the wide locking range, a new frequency detector and the method for optimizing the bias condition of the analog circuit are suggested. An application example to the clocking circuits of a DDR SDRAM is simulated and demonstrated in a 0.6 ${\mu}{\textrm}{m}$ n-well double-poly double-metal CMOS technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.357-360
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• 2013

A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a $0.18-{\mu}m$ 1-poly 6-metal CMOS with a 1.8V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gbps. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.31-38
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• 2005

The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.12
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• pp.141-146
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• 2016

HEVC/H.265 is the latest joint video coding standard proposed by ITU-T SG 16 WP and ISO/IEC JTC 1/SC29/WG 11. In H.265, pictures are divided into a sequence of coding tree units(CTUs), and the CTU further is partitioned into multiple CUs to adapt to various local characteristics. Its coding efficiency is approximately two times high compared to previous standard H.264/AVC. However according to the size of extended CU(coding unit) and transform block, the hardware size of PMR(prediction/mode decision/reconstruction) block within video encoder is about 4 times larger than previous standard. In this study, we propose a new less complex hardware architecture of PMR block which has the most high complexity within encoder without any noticeable PSNR loss. Using this simplified block, we can shrink the overall size the H.265 encoder. For FHD image, it operates at clocking frequency of 300 MHz and frame rate of 60 fps. And also for the test image, the Bjøntegaard Delta (BD) bit rate increase about average 30 % in PMR prediction block, and the total estimated gate count of PMR block is around 1.8 M.