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http://dx.doi.org/10.9723/jksiis.2013.18.5.025

A 2-Gb/s SLVS Transmitter for MIPI D-PHY  

Baek, Seung Wuk (금오공과대학교 전자공학과)
Jeong, Dong Gil (금오공과대학교 전자공학과)
Park, Sang Min (금오공과대학교 전자공학과)
Hwang, Yu Jeong (금오공과대학교 전자공학과)
Jang, Young Chan (금오공과대학교 전자공학과)
Publication Information
Journal of Korea Society of Industrial Information Systems / v.18, no.5, 2013 , pp. 25-32 More about this Journal
Abstract
A 1.8V 2-Gb/s scalable low voltage signaling (SLVS) transmitter (TX) is designed for mobile applications requiring high speed and low power consumption. It consists of 4-lane TX for data transmission, 1-lane TX for a source synchronous clocking, and a 8-phase clock generator. The proposed SLVS TX has the scaling voltage swing from 50 mV to 650 mV and supports a high speed (HS) mode and a low power (LP) mode. An output impedance calibration scheme for the SVLS TX is proposed to improve the signal integrity. The proposed SLVS TX is implemented by using a 0.18-${\mu}m$ 1-poly 6-metal CMOS with a 1.8 V supply. The simulated data jitter of the implemented SLVS TX is about 8.04 ps at the data rate of 2-Gb/s. The area and power consumption of the 1-lane of the proposed SLVS TX are $422{\times}474{\mu}m^2$ and 5.35 mW/Gb/s, respectively.
Keywords
SLVS; output impedance calibration; high speed mode; low power mode;
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1 K.-L. J. Wong, H. Hatamkhani, M. Mansuri, and C.-K. K. Yang, "A 27-mW 3.6-Gb/s I/O transceiver," IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 602-612, Dec. 2004.   DOI   ScienceOn
2 G. Balamurugan, J. Kennedy, G. Banerjee, J. E. Jaussi, M. Mansuri, F.O'Mahony, B. Casper, and R. Mooney, "A scalable 5-15 Gbps, 14-75 mW low-power I/O transceiver in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 1010-1019, Apr. 2008.   DOI   ScienceOn
3 J. Poulton, et. al., "A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS," IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2745-2757, Dec. 2007.   DOI   ScienceOn
4 B. Leibowitz, et. al., "A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling," IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 889-898, Apr. 2010.   DOI   ScienceOn
5 K. Kaviani, et. al., "A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration," ISSCC Dig. Tech Papers, pp.132-133, Feb. 2012
6 A. Amirkhany, J. Wei, N. Mishra, J. Shen, W. Beyene, T. Chin, C. Huang, V. Gadde, K. Kaviani, P. Le, M. M, C. Madden, S. Mukherjee, L. Raghavan, K. Saito, D. Secker, F. Shuaeb, S. Srinivas, T. Wu, C. Tran, A. Vaidyanathan, K. Vyas, M. Jain, K. Chang, and C. Yuan, "A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface for Graphics Applications," Symp. VLSI Circuits, Dig. Tech. Papers, pp.232-233, Jun. 2011.