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A CDR using 1/4-rate Clock based on Dual-Interpolator  

Ahn, Hee-Sun (Division of Electronics & Information Engineering, Chonbuk National University)
Park, Won-Ki (Korea Electronics Technology Institute)
Lee, Sung-Chul (Korea Electronics Technology Institute)
Jeong, Hang-Geun (Division of Electronics & Information Engineering, Chonbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.46, no.1, 2009 , pp. 68-75 More about this Journal
Abstract
In this paper, an efficient proposed CDR(Clock and Data Recovery Circuits) using 1/4-rate clock based on dual-interpolator is proposed. The CDR is aimed to overcome problems that using multi-phase clock to decrease the clock generator frequency causes side effects such as the increased power dissipation and hardware complexity, especially when the number of channels is high. To solve these problems, each recovery part generates needed additional clocks using only inverters, but not flip-flops while maintaining the number of clocks supplied from a clock generator the same as 1/2-rate clock method. Thus, the reduction of a clock generator frequency using 1/4-rate clocking helps relax the speed limitation and power dissipation when higher data rate transfer is demanded.
Keywords
CDR(Clock Data Recovery); Transceiver; Interpolator;
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