A CDR using 1/4-rate Clock based on Dual-Interpolator |
Ahn, Hee-Sun
(Division of Electronics & Information Engineering, Chonbuk National University)
Park, Won-Ki (Korea Electronics Technology Institute) Lee, Sung-Chul (Korea Electronics Technology Institute) Jeong, Hang-Geun (Division of Electronics & Information Engineering, Chonbuk National University) |
1 | B. Garlepp, et al., 'A portable digital DLL for high-speed CMOS interface circuits,' IEEE J. of Solid-State Circuits, Vol. 29, pp. 1491-1496, Dec. 1994 DOI ScienceOn |
2 | Fuji Yang, Joseph Othmer, et al., 'A CMOS low-power multiple 2.5-3.125Gb/s serial link macrocell for high IO bandwidth network ICs,' IEEE J. of Solid-State Circuits, Vol. 37, no. 12, Dec. 2002 DOI ScienceOn |
3 | Rainer Kreienkamp, Hubert Siedhoff, et al., 'A 10-Gb/s CMOS clock and data recovery with an analog phase interpolator,' IEEE J. of Solid-State Circuits, no. 3, Mar. 2005 DOI ScienceOn |
4 | Kun-Yung Ken Chang, Stefanos Sidiropoulos, et al., 'A 0.4-4-Gb/s CMOS quad transceiver cell Using on-chip regulated dual-loop PLLs,' IEEE J. of Solid-State Circuits, Vol. 38, no. 5, May 2003 DOI ScienceOn |
5 | Seong-Jun Song, et al., 'A 4-Gb/s CMOS Clock and Data Recovery Circuit Using 1/8-Rate Clock Technique' IEEE J. of Solid-State Circuits, Vol. 38, 1213-1219, JULY. 2003 DOI ScienceOn |