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A UTMI-Compatible USB2.0 Transceiver Chip Design  

Nam Jang-Jin (High Speed CMOS IC Laboratory, POSTECH)
Kim Bong-Jin (High Speed CMOS IC Laboratory, POSTECH)
Park Hong-June (High Speed CMOS IC Laboratory, POSTECH)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.5, 2005 , pp. 31-38 More about this Journal
Abstract
The architecture and the implementation details of a UTMI(USB2.0 Transceiver Macrocell Interface) compatible USB2.0 transceiver chip were presented. To confirm the validation of the incoming data in noisy channel environment, a squelch state detector and a current mode Schmitt-trigger circuit were proposed. A current mode output driver to transmit 480Mbps data on the USB cable was designed and an on-die termination(ODT) which is controlled by a replica bias circuit was presented. In the USB system using plesiochronous clocking, to compensate for the frequency difference between a transmitter and a receiver, a synchronizer using clock data recovery circuit and FIFO was designed. The USB cable was modeled as the lossy transmission line model(W model) for circuit simulation by using a network analyzer measurements. The USB2.0 PHY chip was implemented by using 0.25um CMOS process and test results were presented. The core area excluding the IO pads was $0.91{\times}1.82mm^2$. The power consumptions at the supply voltage of 2.5V were 245mW and 150mW for high-speed and full-speed operations, respectively.
Keywords
USB2.0; CMOS transceiver; envelope detector; clock data recovery(CDR);
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