JSTS:Journal of Semiconductor Technology and Science

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A 4x Time-Domain Interpolation 6-bit 3.4 GS/s 12.6 mW Flash ADC in 65 nm CMOS

  • Liu, Jianwei (State Key Laboratory of Analog and Mixed-Signal VLSI) ;
  • Chan, Chi-Hang (State Key Laboratory of Analog and Mixed-Signal VLSI) ;
  • Sin, Sai-Weng (State Key Laboratory of Analog and Mixed-Signal VLSI) ;
  • U, Seng-Pan (State Key Laboratory of Analog and Mixed-Signal VLSI) ;
  • Martins, Rui Paulo (State Key Laboratory of Analog and Mixed-Signal VLSI)
  • Received : 2016.02.28
  • Accepted : 2016.05.02
  • Published : 2016.08.30
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Abstract

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

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References

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