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http://dx.doi.org/10.13067/JKIECS.2015.10.8.883

Measurement of Setup and Hold Time in a CMOS DFF for a Synchronizer  

Kim, Kang-Chul (전남대학교 전기전자통신컴퓨터공학부)
Publication Information
The Journal of the Korea institute of electronic communication sciences / v.10, no.8, 2015 , pp. 883-890 More about this Journal
Abstract
As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.
Keywords
Gals; Setup Time; Hold Time; Metastability;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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