• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.1
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• pp.68-75
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• 2009

In this paper, an efficient proposed CDR(Clock and Data Recovery Circuits) using 1/4-rate clock based on dual-interpolator is proposed. The CDR is aimed to overcome problems that using multi-phase clock to decrease the clock generator frequency causes side effects such as the increased power dissipation and hardware complexity, especially when the number of channels is high. To solve these problems, each recovery part generates needed additional clocks using only inverters, but not flip-flops while maintaining the number of clocks supplied from a clock generator the same as 1/2-rate clock method. Thus, the reduction of a clock generator frequency using 1/4-rate clocking helps relax the speed limitation and power dissipation when higher data rate transfer is demanded.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.63-70
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• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.17-22
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• 2012

A novel Clock Generator with jitter suppressed delay-locked loop (DLL) has been proposed to generate highly accurate output signals. The proposed Clock Generator has a VCDL which can suppress its jitter by generating control signals proportional to phase differences among delay stages. It has been designed to generate 1GHz output at 100MHz input with 1.8V $0.18{\mu}m$ CMOS process. The simulation result demonstrates a 3.24ps of peak-to-peak jitter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.446-455
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• 2001

In this paper, the precise synchronized clock generator using GPS receiver is presented. The GPS receiver provides a synchronized IPPS signal which guaranties a reliable standard time mark. This signal allows us to do time synchronization and correct the time step. We designed and implemented the precise synchronized clock generator based on DPLL in order to generate a high-resolution clock from a low-cost inaccurate oscillator with ALTERA FLEX EPM6016TC144-3. We also implemented a hardware unit and proved that the unit provides 1MHz clock output which had a high resolution and accuracy when it was combined with GPS receiver.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1606-1616
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• 1989

In this paper, the design of DYNAMIC CMOS ARRAY LOGIC which has both advantages of dynamic CMOS and array logic circuits is proposed. The major components of DYNAMIC CMOS ARRAY LOGIC are two-stage dunamic CMOS circuits and an internal clock generator. The function block of dynamic CMOS circuits is realized as a parallel interconnection of NMOS transistors. Therefore the operating speed of DYNAMIC CMOS ARRAY LOGIC is much faster than the one of the conventional dynamic CMOS PLAs and static CMOS PLA. Also, the charge redistribution problem by internl delay is solved. The internal clock generator generates four internal clocks that drive all the dynamic CMOS circuits. During evaluation, two clocks of them are delayed as compared with others. Therefore the race problem is completoly eliminated. The internal clock generator also prevents the reduction of circuit output voltage and noise margin due to leakage current and charge coupling without any penalty in circuit operating speed or chip area utilization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.285-291
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• 2001

An 8-b$\times$8-b adiabatic pipelined multiplier is designed. Simplified four phase clock generator is also designed to provide supply clocks for adiabatic circuits. All the clock line charge on the capacitive interconnections is recovered to save energy. Adiabatic circuits are designed based on ECRL(efficient charge recovery logic) and are integrated using 0.6${\mu}{\textrm}{m}$ CMOS technology. The efficiency of proposed supply clock generator is better than the previous one by 4~11%. Simulation results show that the power consumption of adiabatic pipelined multiplier is reduced by a factor of 2.6~3.5 compared to a conventional pipelined CMOS multiplier.

• Journal of IKEEE
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• v.15 no.2
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• pp.129-133
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• 2011

A spread spectrum clock generation is an efficient way to reduce electro-magnetic interference (EMI) radiation in modern mixed signal chip systems. The proposed circuit generates the spread spectrum clock by directly injecting the modulation voltage into the voltage-controlled oscillator (VCO) current source for SATA II. The resulting 33KHz modulation profile has a Hersey-Kiss shape with a rounded peak. The chip has been fabricated using $0.18{\mu}m$ CMOS process and test results show that the proposed circuit achieves 0.509% (5090ppm) down spreading at 1.5GHz and peak power reduction of 10dB. The active chip area is 0.36mm ${\times}$ 0.49mm and the chip consumes 30mW power at 1.5GHz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.282-290
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• 2013

This paper describes a spread spectrum clock generator (SSCG) circuit for DisplayPort 1.2 standard. A Hershey-Kiss modulation profile is generated by dual sigma-delta modulators. The structure generates various modulation slopes to shape a non-linear modulation profile. The proposed SSCG for DisplayPort 1.2 generates clock signals with 5000 ppm down spreading with a Hershey-Kiss modulation profile at three different clock frequencies, 540 MHz, 270 MHz and 162 MHz. The measured peak power reduction is about 15.6 dB at 540 MHz with the chip fabricated using a $0.13{\mu}m$ CMOS technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.776-780
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• 2007

In this paper, the charge pump circuit of a VPP generator for a low voltage DRAM is newly proposed. The proposed charge pump is a 2-stage cross coupled charge pump circuit. The charge transfer efficiency is improved, and Distributed Clock Inverter is located in each charge pump stage to reduce clock period so that the pumping current is increased. In addition, the precharge circuit is located at Gate node of charge transfer transistor to solve the problem which is that the Gate node is maintained high voltage because the boosted charge can't discharge, so device reliability is decreased. The simulation result is that pumping current, pumping efficiency and power efficiency is improved. The layout of the proposed VPP generator is designed using $0.18{\mu}m$ Triple-Well process.