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http://dx.doi.org/10.5573/ieie.2014.51.6.063

A Low-N Phase Locked Loop Clock Generator with Delay-Variance Voltage Converter and Frequency Multiplier  

Choi, Young-Shig (Department of Electronic Engineering, Pukyong National University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.6, 2014 , pp. 63-70 More about this Journal
Abstract
A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.
Keywords
PLL; Clock Generator; low jitter;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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