A VPP Generator Design for a Low Voltage DRAM

저전압 DRAM용 VPP Generator 설계

In this paper, the charge pump circuit of a VPP generator for a low voltage DRAM is newly proposed. The proposed charge pump is a 2-stage cross coupled charge pump circuit. The charge transfer efficiency is improved, and Distributed Clock Inverter is located in each charge pump stage to reduce clock period so that the pumping current is increased. In addition, the precharge circuit is located at Gate node of charge transfer transistor to solve the problem which is that the Gate node is maintained high voltage because the boosted charge can't discharge, so device reliability is decreased. The simulation result is that pumping current, pumping efficiency and power efficiency is improved. The layout of the proposed VPP generator is designed using $0.18{\mu}m$ Triple-Well process.

본 논문에서는 저전압 DRAM용 VPP Generator의 전하펌프회로(Charge Pump Circuit)를 새롭게 제안하였다. 제안된 전하펌프회로는 2-Stage 크로스 커플 전하펌프회로(Cross-Coupled Charge Pump Circuit)이다. 4개의 비중첩 클럭신호들을 이용하여 전하전달 효율을 향상시켰고, 각 전하펌프단 마다 Oscillation 주기를 줄일 목적으로 Distributed Clock Driver인 Inverter 4개를 추가하여 펌핑전류(Pumping Current)를 증가시켰다. 그리고 전하전달 트랜지스터의 게이트단에 프리차지회로 (Precharge Circuit)를 두어 대기모드진입 시 펌핑된 전하를 방전하지 못하고 고전압을 유지하여 소자의 신뢰성을 떨어트리는 문제를 해결하였다. 모의실험결과 펌핑전류, 펌핑효율(Pumping Efficiency), 파워효율(Power Efficiency) 모두 향상된 것을 확인하였고, $0.18{\mu}m$ Triple-Well 공정을 이용하여 Layout 하였다.