A DLL-Based Multi-Clock Generator Having Fast-Relocking and Duty-Cycle Correction Scheme for Low Power and High Speed VLSIs |
Hwang Tae-Jin
(Department of Electronic Engineering, Soongsil University)
Yeon Gyu-Sung (Department of Electronic Engineering, Soongsil University) Jun Chi-Hoon (Department of Electronic Engineering, Soongsil University) Wee Jae-Kyung (Department of Electronic Engineering, Soongsil University) |
1 | T. H. Lee, K. S. Donnelly, J. T. C. Ho, .J. Zerbe, M. G. Johnson, T. Ishikawa, 'A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM', IEEE Journal of Solid-State Circuits, vol.29, pp. 1491-1496, Dec 1994 DOI ScienceOn |
2 | Mark A. Horowitz, et al. 'A Semi digital Dual Delay-Locked Loop', IEEE Journal of Solid-State Circuits, vol. 32, NO.11, Nov 1997 |
3 | C. W. Kim, et al., 'A Low-Power all-Area 7.28-ps-Jitter 1-GHz DLL-Based Clock Generator' IEEE Journal of Solid-State Circuits, vol. 37, NO. 11, Nov 2002 |
4 | T. Gawa, K. Taniguchi, ; 'A 50% Duty-Cycle Correction Circuit for PLL Output', IEEE International Symposium on Circuits and Systems, vol. 4, pp. 26-29 May 2002 DOI |
5 | Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Yunho Choi, Hyung Kyu Lim, 'A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL' IEEE Journal of Solid-State Circuits, vol. 32, pp. 691-700, May 1997 DOI ScienceOn |
6 | F. Anceau., 'A synchronous approach for clocking VLSI systems', IEEE Journal of Solid-State Circuits, vol 17, pp. 51-56, Feb 1982 DOI ScienceOn |
7 | J. Rabaey, Digital Integrated Circuits. Prentice-Hall, 1996 |
8 | I. W. Young, J. K. Wong, 'A PLL clock generator with 5 to 110MHz of lock range for microprocessors' IEEE Journal of Solid-State Circuits, vol. 27, pp.1599-1607, Nov 1992 DOI ScienceOn |