• Title/Summary/Keyword: Channel thickness

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A 2-D Model for the Potential Distribution and Threshold Voltage of Fully Depleted Short-Channel Ion-Implanted Silicon MESFET's

  • Jit, S.;Morarka, Saurabh;Mishra, Saurabh
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.3
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    • pp.173-181
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    • 2005
  • A new two dimensional (2-D) model for the potential distribution of fully depleted short-channel ion-implanted silicon MESFET's has been presented in this paper. The solution of the 2-D Poisson's equation has been considered as the superposition of the solutions of 1-D Poisson's equation in the lateral direction and the 2-D homogeneous Laplace equation with suitable boundary conditions. The minimum bottom potential at the interface of the depletion region due to the metal-semiconductor junction at the Schottky gate and depletion region due to the substrate-channel junction has been used to investigate the drain-induced barrier lowering (DIBL) and its effects on the threshold voltage of the device. Numerical results have been presented for the potential distribution and threshold voltage for different parameters such as the channel length, drain-source voltage, and implanted-dose and silicon film thickness.

Breakdown Characteristics of Silicon Nanowire N-channel GAA MOSFET (실리콘 나노와이어 N-채널 GAA MOSFET의 항복특성)

  • Ryu, In Sang;Kim, Bo Mi;Lee, Ye Lin;Park, Jong Tae
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.20 no.9
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    • pp.1771-1777
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    • 2016
  • In this thesis, the breakdown voltage characteristics of silicon nanowire N-channel GAA MOSFETs were analyzed through experiments and 3-dimensional device simulation. GAA MOSFETs with the gate length of 250nm, the gate dielectrics thickness of 6nm and the channel width ranged from 400nm to 3.2um were used. The breakdown voltage was decreased with increasing gate voltage but it was increased at high gate voltage. The decrease of breakdown voltage with increasing channel width is believed due to the increased current gain of parasitic transistor, which was resulted from the increased potential in channel center through floating body effects. When the positive charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was decreased due to the increased potential in channel center. When the negative charge was trapped into the gate dielectrics after gate stress, the breakdown voltage was increased due to the decreased potential in channel center. We confirmed that the measurement results were agreed with the device simulation results.

An Analytical Model for the Threshold Voltage of Short-Channel Double-Material-Gate (DMG) MOSFETs with a Strained-Silicon (s-Si) Channel on Silicon-Germanium (SiGe) Substrates

  • Bhushan, Shiv;Sarangi, Santunu;Gopi, Krishna Saramekala;Santra, Abirmoya;Dubey, Sarvesh;Tiwari, Pramod Kumar
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.4
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    • pp.367-380
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    • 2013
  • In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.

A Study on Breakdown Voltage of Double Gate MOSFET (DGMOSFET의 항복전압에 관한 연구)

  • Jung, Hak-Kee
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.05a
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    • pp.693-695
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    • 2012
  • This paper have presented the breakdown voltage for double gate(DG) MOSFET. The analytical solution of Poisson's equation and Fulop's breakdown condition have been used to analyze for breakdown voltage. The double gate(DG) MOSFET as the device to be able to use until nano scale has the adventage to reduce the short channel effects. But we need the study for the breakdown voltage of DGMOSFET since the decrease of the breakdown voltage is unavoidable. To approximate with experimental values, we have used the Gaussian function as charge distribution for Poisson's equation, and the change of breakdown voltage has been observed for device geometry. Since this potential model has been verified in the previous papers, we have used this model to analyze the breakdown voltage. As a result to observe the breakdown voltage, the smaller channel length and the higher doping concentration become, the smaller the breakdown voltage becomes. Also we have observed the change od the breakdown voltage for gate oxide thickness and channel thickness.

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A Study of Ice-Formation Phenomena on Freezing of Flowing Water in a Stenotic Tube

  • Suh, Jeong-Se;Kim, Moo-Geun;Ro, Sung-Tack;Yim, Chang-Soon
    • International Journal of Air-Conditioning and Refrigeration
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    • v.7
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    • pp.1-10
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    • 1999
  • In this study, a numerical analysis is made on the ice-formation for laminar water flow inside a stenotic tube. The study takes into account the interaction between the laminar flow and the stenotic port in the circular tube. The purpose of the present numerical investigation is to assess the effect of a stenotic shape on the instantaneous shape of the flow passage during freezing upstream/downstream of the stenotic channel. In the solution strategy, the present study is substantially distinguished from the existing works in that the complete set of governing equations in both the solid and liquid regions are resolved. In a channel flow between parallel plates, the agreement between the of predictions and the available experimental data is very good. Numerical analyses are performed for parametric variations of the position and heights of stenotic shape and flow rate. The results show that the stenotic shape has the great effect on the thickness of the solidification layer inside the tube. As the height of a stenosis grows and the length of a stenosis decreases, the ice layer thickness near the stenotic port is thinner, due to backward flow caused by the sudden expansion of a water tunnel. It is found that the flow passage has a slight uniform taper up to the stenotic channel, at which a sudden expansion is observed. It is also shown that the ice layer becomes more fat in accordance with its Reynolds number.

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Microstructural Evolution of Cu-15 wt%Ag Composites Processed by Equal Channel Angular Pressing (등통로각압축공정을 이용하여 제조된 Cu-15 wt%Ag 복합재의 미세구조)

  • Lee, In Ho;Hong, Sun Ig;Lee, Kap Ho
    • Korean Journal of Metals and Materials
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    • v.50 no.12
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    • pp.931-937
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    • 2012
  • The microstructure of Cu-15 wt%Ag composites fabricated by equal channel angular pressing (ECAP) with intermediate heat treatment at $320^{\circ}C$ was investigated by transmission electron microscopy (TEM) observations. Ag precipitates with a thickness of 20-40 nm were observed in the eutectic region of the Cu-15 wt%Ag composite solution treated at $700^{\circ}C$ before ECAP. The Cu matrix and Ag precipitates had a cube on cube orientation relationship. ECAPed composites exhibited ultrafine-grained microstructures with the shape and distribution dependent on the processing routes. For route A in which the sample was pressed without rotation between each pass, the Cu and Ag grains were elongated along the shear direction and many micro-twins were observed in elongated Cu grains as well as in Ag filaments. The steps were observed on coherent twin boundaries in Cu grains. For route Bc in which the sample was rotated by 90 degrees after each pass, a subgrain structure with misorientation of 2-4 degree by fragmentation of the large Cu grains were observed. For route C in which the sample was rotated by 180 degrees after each pass, the microstructure was similar to that of the route A sample. However, the thickness of the elongated grains along the shear direction was wider than that of the route A sample and the twin density was lower than the route A sample. It was found that more microtwins were formed in ECAPed Cu-15 wt%Ag than in the drawn sample. Grain boundaries were observed in relatively thick and long Ag filaments in Cu-15 wt%Ag ECAPed by route C, indicating the multi-crystalline nature of Ag filaments.

Impact of Remanent Polarization and Coercive Field on Threshold Voltage and Drain-Induced Barrier Lowering in NCFET (negative capacitance FET) (NCFET (negative capacitance FET)에서 잔류분극과 항전계가 문턱전압과 드레인 유도장벽 감소에 미치는 영향)

  • Hakkee Jung
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.37 no.1
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    • pp.48-55
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    • 2024
  • The changes in threshold voltage and DIBL were investigated for changes in remanent polarization Pr and coercive field Ec, which determine the characteristics of the P-E hysteresis curve of ferroelectric in NCFET (negative capacitance FET). The threshold voltage and DIBL (drain-induced barrier lowering) were observed for a junctionless double gate MOSFET using a gate oxide structure of MFMIS (metal-ferroelectric-metal-insulator-semiconductor). To obtain the threshold voltage, series-type potential distribution and second derivative method were used. As a result, it can be seen that the threshold voltage increases when Pr decreases and Ec increases, and the threshold voltage is also maintained constant when the Pr/Ec is constant. However, as the drain voltage increases, the threshold voltage changes significantly according to Pr/Ec, so the DIBL greatly changes for Pr/Ec. In other words, when Pr/Ec=15 pF/cm, DIBL showed a negative value regardless of the channel length under the conditions of ferroelectric thickness of 10 nm and SiO2 thickness of 1 nm. The DIBL value was in the negative or positive range for the channel length when the Pr/Ec is 25 pF/cm or more under the same conditions, so the condition of DIBL=0 could be obtained. As such, the optimal condition to reduce short channel effects can be obtained since the threshold voltage and DIBL can be adjusted according to the device dimension of NCFET and the Pr and Ec of ferroelectric.

Dependency of Phonon-limited Electron Mobility on Si Thickness in Strained SGOI (Silicon Germanium on Insulator) n-MOSFET (Strained SGOI n-MOSFET에서의 phonon-limited전자이동도의 Si두께 의존성)

  • Shim Tae-Hun;Park Jea-Gun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.9 s.339
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    • pp.9-18
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    • 2005
  • To make high-performance, low-power transistors beyond the technology node of 60 nm complementary metal-oxide-semiconductor field-effect transistors(C-MOSFETs) possible, the effect of electron mobility of the thickness of strained Si grown on a relaxed SiGe/SiO2/Si was investigated from the viewpoint of mobility enhancement via two approaches. First the parameters for the inter-valley phonon scattering model were optimized. Second, theoretical calculation of the electronic states of the two-fold and four-fold valleys in the strained Si inversion layer were performed, including such characteristics as the energy band diagrams, electron populations, electron concentrations, phonon scattering rate, and phonon-limited electron mobility. The electron mobility in an silicon germanium on insulator(SGOI) n-MOSFET was observed to be about 1.5 to 1.7 times higher than that of a conventional silicon on insulator(SOI) n-MOSFET over the whole range of Si thickness in the SOI structure. This trend was good consistent with our experimental results. In Particular, it was observed that when the strained Si thickness was decreased below 10 nm, the phonon-limited electron mobility in an SGOI n-MOSFT with a Si channel thickness of less than 6 nm differed significantly from that of the conventional SOI n-MOSFET. It can be attributed this difference that some electrons in the strained SGOI n-MOSFET inversion layer tunnelled into the SiGe layer, whereas carrier confinement occurred in the conventional SOI n-MOSFET. In addition, we confirmed that in the Si thickness range of from 10 nm to 3 nm the Phonon-limited electron mobility in an SGOI n-MOSFET was governed by the inter-valley Phonon scattering rate. This result indicates that a fully depleted C-MOSFET with a channel length of less than 15 m should be fabricated on an strained Si SGOI structure in order to obtain a higher drain current.

Conduction Path Dependent Threshold Voltage for the Ratio of Top and Bottom Oxide Thickness of Asymmetric Double Gate MOSFET (비대칭 이중게이트 MOSFET의 상하단 산화막 두께비에 따른 전도중심에 대한 문턱전압 의존성)

  • Jung, Hakkee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.18 no.11
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    • pp.2709-2714
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    • 2014
  • This paper has analyzed the change of threshold voltage and conduction path for the ratio of top and bottom gate oxide thickness of asymmetric double gate MOSFET. The asymmetric double gate MOSFET has the advantage that the factor to be able to control the current in the subthreshold region increases. The analytical potential distribution is derived from Poisson's equation to analyze the threshold voltage and conduction path for the ratio of top and bottom gate oxide thickness. The Gaussian distribution function is used as charge distribution. This analytical potential distribution is used to derive off-current and subthreshold swing. By observing the results of threshold voltage and conduction path with parameters of bottom gate voltage, channel length and thickness, projected range and standard projected deviation, the threshold voltage greatly changed for the ratio of top and bottom gate oxide thickness. The threshold voltage changed for the ratio of channel length and thickness, not the absolute values of those, and it increased when conduction path moved toward top gate. The threshold voltage and conduction path changed more greatly for projected range than standard projected deviation.

Analysis of Subthreshold Characteristics for DGMOSFET according to Oxide Thickness Using Nonuniform Doping Distribution (비선형도핑분포를 이용한 DGMOSFET의 산화막두께에 대한 문턱전압이하 특성분석)

  • Jung, Hak-Kee
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.7
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    • pp.1537-1542
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    • 2011
  • In this paper, the subthreshold characteristics have been analyzed for various oxide thickness of double gate MOSFET(DGMOSFET) using Poisson's equation with nonuniform doping distribution. The DGMOSFET is extensively been studying since it can shrink the short channel effects(SCEs) in nano device. The degradation of subthreshold swing(SS) known as SCEs has been presented using analytical for, of Poisson's equation with nonuniform doping distribution for DGMOSFET. The SS have been analyzed for, change of gate oxide thickness to be the most important structural parameters of DGMOSFET. To verify this potential and transport models of thus analytical Poisson's equation, the results have been compared with those of the numerical Poisson's equation, and subthreshold swing has been analyzed using this models for DGMOSFET.