• 한국전기전자재료학회논문지
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• 제11권6호
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• pp.428-435
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• 1998

SOI-like-bulk CMOS device is proposed, which having the advantages of SOI(Silicon On Insulator) and protects short channel effects efficiently with adding partial epitaxial process at standard CMOS process. SOI-like-bulk NMOS and PMOS with 0.25${\mu}{\textrm}{m}$ gate length have designed and optimized through analyzing the characteristics of these devices and applying again to the design of processes. The threshold voltages of the designed NMOS and PMOS are 0.3[V], -0.35[V] respectively and those have shown the stable characteristics under 1.5[V] gate and drain voltages. The leakage current of typical bulk-CMOS increase with shortening the channel length, but the proposed structures on this a study reduce the leakage current and improve the subthreshold characteristics at the same time. In addition, subthreshold swing value, S is 70.91[mV/decade] in SOI-like-bulk NMOS and 63.37[mV/ decade] SOI-like-bulk PMOS. And the characteristics of SOI-like-bulk CMOS are better than those of standard bulk CMOS. To validate the circuit application, CMOS inverter circuit has designed and transient & DC transfer characteristics are analyzed with mixed mode simulation.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1993년도 추계학술대회 논문집
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• pp.93-96
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• 1993

BiCMOS technology, which combines CMOS and bipolar technology, offers the possibility of achieving both very high density and high performance. In this paper, the characteristics of BiCMOS and CMOS circuits, especilly the delay time is studied. BiCMOS inverter, which has high drive ability because of bipolar transistor, drives high load capacitance and has low-power characteristics because the current flows only during switching transient just like the CMOS gate. BiCMOS inverter has the less dependence on load capacitance than CMOS inverter. SPICE that has been used for electronic circuit analysis is chosen to simulate these circuits and the characteristics is discussed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.253-256
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• 2002

A programmable CMOS negative resistor has been designed and fabricated in a 0.5um double poly double metal technology. The proposed CMOS negative resistor consists of a positive feedback OTA and a bump circuit with Gaussian-like I-V curve. Measurements of the fabricated chip confirm that the proposed CMOS resistor shows various negative resistance according to control voltage.

• 전자공학회논문지
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• 제50권4호
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• pp.65-72
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• 2013

본 논문에서는 멤리스터 기반의 논리 게이트와 멤리스터-CMOS 기반의 프리미티브 IP 설계 방법을 제안하였다. 회로 설계를 위한 멤리스터 모델을 제시하고 멤리스터의 AND 및 OR 연결을 기본으로 멤리스터-CMOS 회로설계를 위한 프리미티브 IP설계 방법을 제안하였고, $0.18{\mu}m$ CMOS 공정과 멤리스터 SPICE 모델을 이용한 시뮬레이션을 통해 검증되었다. 회로는 멤리스터와 CMOS 결합을 하여 레이아웃 설계를 하고 네트리스트를 추출하였다. 디지털 프리미티브 IP들에 대해 기존의 CMOS와 면적비교를 수행하였으며, 멤리스터-CMOS 전가산기는 CMOS 전가산기에 비하여 47.6 %의 면적이 감소되었다.

• 한국통신학회논문지
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• 제29권4A호
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• pp.458-465
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• 2004

본 논문에서는 CMOS 공정을 사용하여 선형적으로 제어가 가능한 П모델 감쇄기를 구현하였고, 브릿지 T모델을 사용한 감쇄기를 제안하였다. CMOS 공정으로 코어의 수동소자를 트랜지스터로 구현하여 기존의 수동소자나 능동소자를 사용하는데 따른 문제점을 개선하였으며 GaAs MESFET공정의 문제점인 높은 비용 또한 해결하였다. П모델 감쇄기는 2-poly 4-metal 0.35$\mu\textrm{m}$ CMOS 공정을 사용하여 구현하였으며 기존의 수백 MHz의 동작 주파수범위를 DC-l㎓ 대역으로 향상시켰다. 또한 700$\mu\textrm{m}$${\times}$300$\mu\textrm{m}$ 로 면적을 줄였으며 일정한 주파수에서 감쇄 값과 제어 전압 사이의 선형적인 관계를 개선하였다. 제안된 브릿지 T모델 감쇄기는 П모델에서 동작주파수를 제한하던 매칭 특성을 향상시킴으로써 동작 주파수 템위를 DC-2㎓ 대역으로 넓혔다.

• 전기학회논문지
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• 제56권7호
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• pp.1282-1287
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• 2007

We investigated the damage of the CMOS IC which manufactured three different technologies by high power microwave. The tests separated the two methods in accordance with the types of the CMOS IC located inner waveguide. The only CMOS IC which was located inner waveguide was occurred breakdown below the max electric field (23.94kV/m) without destruction but the CMOS IC which was connected IC to line organically was located inner waveguide and it was occurred breakdown and destruction below the max electric field. Also destructed CMOS IC was removed their surface and a chip condition was analyzed by SEM. The SEM analysis of the damaged devices showed onchuipwire and bondwire destruction like melting due to thermal effect. The tested results are applied to the fundamental data which interprets the combination mechanism of the semiconductors from artificial electromagnetic wave environment and are applied to the data which understand electromagnetic wave effects of electronic equipments.

• 한국초전도ㆍ저온공학회논문지
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• 제8권1호
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• pp.26-28
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• 2006

The development technique of digital logic using CMOS device is close reached several limitations These make technical needs that are ultra high speed superconductive systems based on CMOS silicon digital computing technique. Comparing digital logic based on silicon CMOS, the computing technique based on ultra high speed superconductive systems has many advantages which are ultra low power consumption, ultra high operation speed. etc. It is estimated that features like these increasingly improve the possibility of ultra low power and ultra superconductive systems. In this paper digital logics of current CMOS technique and RSFQ superconductive technique are compared with and analyzed.

• 한국정밀공학회지
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• 제20권5호
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• pp.218-224
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• 2003

This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.1185-1186
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• 2008

A nuclear explosion emits a transient radiation pulse like gamma rays. Gamma rays have a high energy and cause unexpected effects in semiconductor devices. These effects are mainly referred to dose-rate latcup and dose-rate upset. By transient radiation pulse in CMOS devices, dose-rate latchup is simulated in this paper.

• 대한전자공학회논문지
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• 제26권6호
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• pp.131-139
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• 1989

본 논문에서는 CMOS 및 domino CMOS 의 특징과 PLA등 array logic의 특징을 동시에 살리면서 동작특성이 좋고 집적도가 높으며 테스트 생성이 쉬운 domino CMOS NOR-NOR array logic의 설계방식을 제안하였다. 이 방식은 pull-down 특성을 개선하여 기생 커패시턴트의 문제점을 해결하며 간단한 부가회로를 사용하여 회로내의 모든 고정들을 검출할 수 있도록 한 testable design 방식이다. PLA의 적항군의 개념 및 특성 행렬을 이용한 테스트 생성 알고리듬과 절차를 제안하였고 이를 PASCAL 언어로 실현하였다. 또한 SPICE 및 P-SPICE를 이용하여 본 설계방식에 대한 검증을 행하였다.