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Chip-scale Integration Technique for a Microelectromechnical System on a CMOS Circuit  

Michele Miller (National Institute of Standar ds and Technology, USA)
Tomas G. Bifano (Michigan Technological University, USA)
Publication Information
Journal of the Korean Society for Precision Engineering / v.20, no.5, 2003 , pp. 218-224 More about this Journal
Abstract
This paper describes a novel MEMS integration technique on a CMOS chip. MEMS integration on CMOS circuit has many advantages in view of manufacturing cost and reliability. The surface topography of a CMOS chip from a commercial foundry has 0.9 ${\mu}{\textrm}{m}$ bumps due to the conformal coating on aluminum interconnect patterns, which are used for addressing each MEMS element individually. Therefore, it is necessary to achieve a flat mirror-like CMOS chip fer the microelectromechanical system (MEMS) such as micro mirror array. Such CMOS chip needs an additional thickness of the dielectric passivation layer to ease the subsequent planarization process. To overcome a temperature limit from the aluminum thermal degradation, this study uses RF sputtering of silicon nitride at low temperature and then polishes the CMOS chip together with the surrounding dummy pieces to define a polishing plane. Planarization reduces 0.9 ${\mu}{\textrm}{m}$ of the bumps to less than 25 nm.
Keywords
Integration; MEMS; sputtering; planarization; dielectric layer; CMOS;
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