• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.381-386
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• 2013

A new resistance model for a Schottky Barrier Diode (SBD) in CMOS technology is proposed in this paper. The proposed model includes the n-well thickness as a variable to explain the operational behavior of a planar SBD which is firstly introduced in this paper. The model is verified using the simulation methodology ATLAS. For verification of the analyzed model and the ATLAS simulation results, SBD prototypes are fabricated using a $0.13{\mu}m$ CMOS process. It is demonstrated that the model and simulation results are consistent with measurement results of fabricated SBD.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.851-854
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• 1999

A high efficient, CMOS RF power amplifier at a 2.SV power supply for the band of 902-928MHz was designed and analyzed in 0.25${\mu}{\textrm}{m}$ standard CMOS technology. The output power of designed amplifier is being digitally controlled from a minimum of 2㎽ to a maximum of 21㎽, corresponding to a dynamic range of l0㏈ power control. The frequency response of this power amplifier is centered roughly at 915MHz. The power added efficiency of designed amplifer is almost 48% at maximum output power of 21㎽.

• 센서학회지
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• 제17권1호
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• pp.35-40
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• 2008

Low power bridge type micro gas sensors were fabricated by micro machining technology with TMAH (Tetra Methyl Ammonium Hydroxide) solution. The sensing devices with different heater materials such as metal and poly-silicon were obtained using CMOS (Complementary Metal Oxide Semiconductor) compatible process. The tellurium films as a sensing layer were deposited on the micro machined substrate using shadow silicon mask. The low power micro gas sensors showed high sensitivity to NO with high speed. The pure tellurium film used micro gas sensor showed good sensitivity than transition metal (Pt, Ti) used tellurium film.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권4호
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• pp.283-288
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• 2008

A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation ($IM_3$) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using $0.18-{\mu}m$ technology. The LNA achieved +10.2 dBm IIP3 with 13.7 dB gain and 1.68 dB NF at 2 GHz consuming 11.8 mA from a 1.8-V supply. It shows IIP3 improvement by 6.6 dB over the conventional cascode LNA without the linearizing circuit.

• 한국항해항만학회지
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• 제36권9호
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• pp.737-740
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• 2012

A miniaturized CMOS bandpass filter for a single RF transceiver system is presented, using diagonally end-shorted coupled lines and lumped capacitors. In contrast to conventional miniaturized coupled line filters, it is proven that the effective permittivity variation of the coupled transmission line has no effect on shifting the center frequency when the bandpass filter is highly miniaturized. A bandpass filter at a center frequency of 2 GHz was fabricated by $0.18{\mu}m$ CMOS technology. The insertion loss with the die area of $1500{\mu}m{\times}1000{\mu}m$ is -5.14 dB. Simulated results are well agreed with the easurements. It also verify the center frequency stability in the compact size bandpass filter.

• 한국전기전자재료학회논문지
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• 제17권10호
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• pp.1029-1033
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• 2004

In this paper, we propose a new Suppressed Sidewall Injection Magnetotransistor(SSIMT) architecture, which allows to overcome the restriction of the standard CMOS technology and achieve high linearity. The proposed SSIMT is designed based on the Hynix 0.6 um standard CMOS technology. The fabricated SSIMT has been experimentally verified. The SSIMT shows that the change of collector current is extremely linear as a function of the magnetic induction at $I_{B}$ =500$\mu$A, $V_{CE}$ =2V and VSE =5 V. The relative sensitivity is up to 120 %/T. The magnetic conversion offset is about 79 mT with 30.5 %/T relative sensitivity. The nonlinearity of the fabricated SSIMT is measured about 1.4 %.%.

• 센서학회지
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• 제18권4호
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• pp.280-285
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• 2009

In this paper, we designed a 2-stage CMOS operational amplifier with temperature compensation function using 2-poly 4-metal 0.35 $\mu$m standard CMOS technology. Using two bias circuits, the positive temperature coefficient(PTC) and the negative temperature coefficient(NTC) of the bias circuit are canceled out each other. When reference current circuit is simulated that it has a temperature coefficient of -150 ppm/$^{\circ}C$ with a temperature change from 0 $^{\circ}C$ to 120 $^{\circ}C$. Also the proposed circuit has a temperature coefficient of -0.011 dB/$^{\circ}C$ of DC open loop gain with the same temperature range.

• 한국전기전자재료학회논문지
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• 제15권12호
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• pp.1021-1026
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• 2002

As the development of semiconductor process technology continue to advance, ICs continue their trend toward higher performance low power system-on-chip (SOC). These circuits require on board multi power supply. In this paper, a 0.5 ㎛ dual date oxide CMOS Process technology for multi-power application is demonstrated. 5 V and 20 V devices fabricated by proposed process is measured. From 5 V devices using dual gate precess, we got almost the same characteristics as are obtained from standard 5 V devices. And the characteristics of the 20 V device demonstrates that 3 ㎛ devices with minimum gate length are available without reliability degradation. Electrical parameters in minimum 3 ㎛ devices are 520 ㎂/㎛ current density, 120 ㎷ DIBL, 24 V BV for NMOS and ,350 ㎂/㎛ current density, 180 ㎷ DIBL, 26 V BV for PMOS, respectively.

• 한국전기전자재료학회논문지
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• 제20권8호
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• pp.697-700
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• 2007

A novel 2-Dimensional Suppressed Sidewall Injection Magnetotransistor (SSIMT) with high linearity has been fabricated on the standard CMOS technology and experimentally verified. The novel 2-Dimensional SSIMT overcomes the restriction of the standard CMOS technology. Experimental results of the fabricated 2-Dimensional SSIMT show that the variation of each collector output currents are extremely linear as a function of magnetic field from -200mT to 200mT at $I_B = 1 mA,\;V_{CE} = 5 V\;and\;V_{SE} = 5 V$. The relative sensitivity shows up to 13 %/T. The measured nonlinearity of the fabricated device is about 0.9%.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.591-592
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• 2006

Schottky diodes for Radio-frequency identification (RFID) tag integration on chip were designed and fabricated using Samsung electronics System LSI standard $0.18{\mu}m$ CMOS process. Schottky diodes were designed as interdigitated fingers array by CMOS layout design rule. 64 types of Schottky diode were designed and fabricated with the variation of finger width, length and numbers with a $0.6{\mu}m$ guard ring enclosing n-well. Titanium was used as Schottky contact metal to lower the Schottky barrier height. Barrier height of the fabricated Schottky diode was 0.57eV. DC current - voltage measurements showed that the fabricated Schottky diode had a good rectifying properties with a breakdown voltage of -9.15 V and a threshold voltage of 0.25 V.