[KSCI] Korea Science Citation Index Service

http://dx.doi.org/10.5573/JSTS.2013.13.4.381

A New Resistance Model for a Schottky Barrier Diode in CMOS Including N-well Thickness Effect

Lee, Jaelin (Department of Electrical Engineering, KAIST)
Kim, Suna (Department of Electrical Engineering, KAIST)
Hong, Jong-Phil (Department of Electrical Engineering, Chungbuk National University)
Lee, Sang-Gug (Department of Electrical Engineering, KAIST)

Publication Information

JSTS:Journal of Semiconductor Technology and Science / v.13, no.4, 2013 , pp. 381-386 More about this Journal

Abstract

A new resistance model for a Schottky Barrier Diode (SBD) in CMOS technology is proposed in this paper. The proposed model includes the n-well thickness as a variable to explain the operational behavior of a planar SBD which is firstly introduced in this paper. The model is verified using the simulation methodology ATLAS. For verification of the analyzed model and the ATLAS simulation results, SBD prototypes are fabricated using a $0.13{\mu}m$ CMOS process. It is demonstrated that the model and simulation results are consistent with measurement results of fabricated SBD.

Keywords

CMOS; capacitance; cut-off frequency; n-well thickness; resistance; Schottky barrier diodes;

Citations & Related Records

Reference

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