A Study on the 0.5μm Dual Gate High Voltage CMOS Process for Si Liquid Display System

As the development of semiconductor process technology continue to advance, ICs continue their trend toward higher performance low power system-on-chip (SOC). These circuits require on board multi power supply. In this paper, a 0.5 ㎛ dual date oxide CMOS Process technology for multi-power application is demonstrated. 5 V and 20 V devices fabricated by proposed process is measured. From 5 V devices using dual gate precess, we got almost the same characteristics as are obtained from standard 5 V devices. And the characteristics of the 20 V device demonstrates that 3 ㎛ devices with minimum gate length are available without reliability degradation. Electrical parameters in minimum 3 ㎛ devices are 520 ㎂/㎛ current density, 120 ㎷ DIBL, 24 V BV for NMOS and ,350 ㎂/㎛ current density, 180 ㎷ DIBL, 26 V BV for PMOS, respectively.

실리콘 액정표시 장치 시스템을 위한 00.5μm 이중 게이트 고전압 CMOS 공정 연구