한국전기전자재료학회논문지 (Journal of the Korean Institute of Electrical and Electronic Material Engineers)

  • 제17권10호
  • /
  • Pages.1029-1033
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  • 2004
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  • 1226-7945(pISSN)
  • /
  • 2288-3258(eISSN)
한국전기전자재료학회 (The Korean Institute of Electrical and Electronic Material Engineers)
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CMOS 공정에 의한 Suppressed Sidewall Injection Magnetotransistor의 특성

Characteristics of the Suppressed Sidewall Injection Magnetotransistor using a CMOS Process

  • 송윤귀 (부경대학교 전자공학과) ;
  • 최영식 (부경대학교 전자공학과) ;
  • 김남호 (부경대학교 제아계측공학과) ;
  • 류지구 (부경대학교 전자공학과)
  • 발행 : 2004.10.01
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초록

In this paper, we propose a new Suppressed Sidewall Injection Magnetotransistor(SSIMT) architecture, which allows to overcome the restriction of the standard CMOS technology and achieve high linearity. The proposed SSIMT is designed based on the Hynix 0.6 um standard CMOS technology. The fabricated SSIMT has been experimentally verified. The SSIMT shows that the change of collector current is extremely linear as a function of the magnetic induction at $I_{B}$ =500$\mu$A, $V_{CE}$ =2V and VSE =5 V. The relative sensitivity is up to 120 %/T. The magnetic conversion offset is about 79 mT with 30.5 %/T relative sensitivity. The nonlinearity of the fabricated SSIMT is measured about 1.4 %.%.

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참고문헌

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