• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.5
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• pp.312-320
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• 2003

This work describes an 8b 200 MHz 0.18 urn CMOS analog-to-digital converter (ADC) based on a pipelined architecture for flat panel display applications. The proposed ABC employs an improved bootstrapping technique to obtain wider input bandwidth than the sampling tate of 200 MHz. The bootstrapuing technique improves the accuracy of the input sample-and-hold amplifier (SHA) and the fast fourier transform (FFT) analysis of the SHA outputs shows the 7.2 effective number of bits with an input sinusoidal wave frequency of 500 MHz and the sampling clock of 200 MHz at a 1.7 V supply voltage. Merged-capacitor switching (MCS) technique increases the sampling rate of the ADC by reducing the number of capacitors required in conventional ADC's by 50 % and minimizes chip area simultaneously. The simulated ADC in a 0.18 um n-well single-poly quad-metal CMOS technology shows an 8b resolution and a 73 mW power dissipation at a 200 MHz sampling clock and a 1.7 V supply voltage.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.4
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• pp.25-35
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• 2002

This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.

• Journal of IKEEE
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• v.21 no.3
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• pp.219-226
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• 2017

This paper was studied the double-band monopole antenna design with Mu-negative metamaterial unit cell, which operates at 700MHz and 2.45GHz band. Mu-negative unit cell made of the interdigital capacitor structure to operate a double-band antenna by inserting it into an antenna radiator unit. In addition, the parasitic conductor is implemented on the back side of the antenna radiation part, so that the resonance point of the antenna can be controlled and the bandwidth is improved. Finally, we implemented an antenna operating in the 750MHz UHD band and the 2.45GHz WiFi band. The designed antenna has a size of $200{\times}100mm^2$. Experimental results show that the 8dB bandwidth and gain characteristics at 750MHz band are 320MHz(42.7%), 5.28dB, 6dB bandwidth and gain at 2.45GH are 540MHz (21.6%), -0.46dB. From the experimental results, we confirmed that the resonance point with theoretical value is in agreement with experimental value, and the radiation patterns are have the omnidirectional characteristic in both bands.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.10
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• pp.69-75
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• 2004

This work proposes an 8b 220 MS/s 230 mW 3-stage pipeline CMOS ADC with on-chip filers for temperature- and power- insensitive voltage references. The proposed RC low-pass filters improve switching noise performance and reduce reference settling time at heavy R & C loads without conventional off-chip large bypass capacitors. The prototype ABC fabricated in a 0.25 um CMOS occupies the active die area of 2.25 $\textrm{mm}^2$ and shows the measured DNL and INL of maximum 0.43 LSB and 0.82 LSB, respectively. The ADC maintains the SNDR of 43 dB and 41 dB up to the 110 MHz input at 200 MS/s and 220 MS/s, respectively, while the SNDR at the 500 MHz input is degraded as much as only 3 dB than the SNDR at the 110 MHz input.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.5
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• pp.568-575
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• 2011

In this paper, we propose a small broadband antenna for mobile device. The proposed antenna consists of a printed rectangular monopole antenna and a parastic element connected to ground using narrow meander line and it is designed on a FR-4 substrate that has a thickness of 0.8 mm and a dielectric constant of 4.4. The FR-4 substrate's size is 50 mm${\times}$90 mm comparable to the real mobile device. The fabricated antenna's size is 12.5 mm${\times}$10.5 mm${\times}$0.8 mm and the measurement shows -10 dB return loss bandwidth of 2,200~6,000 MHz and gains of 2.86~4.01 dBi. Accordingly, the proposed antenna can support mobile device for WiBro(2,300~2,380 MHz), WLAN(IEEE 802.11b/g/n: 2,400~2,480 MHz, IEEE 802.11a: 5,150~5,825 MHz), and mobile WiMAX(IEEE 802.16e : 2,500~2,690 MHz, 3,400~3,600 MHz) service bands.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.2 s.117
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• pp.151-157
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• 2007

We have presented a compact two-wire helical antenna adopted an open stub in opposite to a feeding point, which is for a T-DMB antenna of mobile devices. By adjusting the length of the open stub or pasting a dielectric material on the open stub, the input impedance around 200 MHz, bands of the T-DMB, can be easily control, even though the total height of the antenna is less than 8 cm(0.053 $\lambda$ at 200 MHz). The operating mechanism of the antenna is explained by using equivalent circuits of two modes, an unbalanced mode and a balanced mode. Based on the analysis of the equivalent circuits, the effects of using the open stub are validated. Several proposed antennas have been fabricated and measured. One of the fabricated antennas has -10 dB impedance bandwidth of $196{\sim}204$ MHz(8 MHz) whose value covers one channel of the T-DMB(6 MHz). The measured $S_{21}$ of the antenna is -38.6 dB which is about 17 dB higher than that of a monopole antenna whose height is same with the proposed antenna.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.39-45
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• 2011

This paper proposes a low power current-steering 10-bit DAC selecting clock enable signal. The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in wihich the data will not be changed. The proposed DAC was implemented using a 0.13${\mu}m$ CMOS process with $V_{DD}=1.2V$. Its core area is 0.21$mm^2$. It consumes 4.46mW at 1MHz signal frequency and 200MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25MHz and 10MHz signal frequencies, respectively. The measured SFDRs are 72.8dB and 56.1dB at 1MHz and 50MHz signal frequencies, respectively.

• ETRI Journal
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• v.35 no.1
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• pp.158-161
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• 2013

This letter proposes a low-power current-steering digital-to-analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in which the data will not be changed. The 10-bit DAC is implemented using a $0.13-{\mu}m$ CMOS process with $V_{DD}$=1.2 V. Its area is $0.21\;mm^2$. It consumes 4.46 mW at a 1-MHz signal frequency and 200-MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25-MHz and 10-MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1-MHz and 50-MHz signal frequencies, respectively.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.983-986
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• 2003

This paper describes a 2.5V 80dB 360MHz CMOS VGA. A new variable degeneration resistor is proposed where the dc voltage drop over the degeneration resistor is minimized and employed in designing a low-voltage and high-speed CMOS VGA. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than 1.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$$\times$360${\mu}{\textrm}{m}$.

• Journal of the Korean Vacuum Society
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• v.4 no.4
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• pp.413-416
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• 1995

고주파 마그네트론 스펏터링법을 이용하여 ZnO막을 제조하고 유리기판 위에 ZnO-SAW필터를 제작하였다. ZnO막의 제조 조건은 고주파 전력 150W, 기판온도 $200^{\circ}C$, 분위기압 5mTorr 및 O2/(Ar+O2)비 50%였다. 한편 IDT(Inter-digital transducer)전극은 전극 폭을 2.56mm, 전극 거리를 2,936mm, λ/8폭을 $8mu$m로 설계하였다. 제작된 ZnO-SAW필터의 주파수 응답을 측정하기 위해 소자는 mount(TO8)에 고정시켰다. ZnO SAW필터의 통과 대역(3 dB대역폭)은 345.2~44.8 MHz로 9.6MHz의 대역 폭을 나타내었으며 중심주 파수는 40 MHz를 나타내었다. 또한 삽입 손실은 39 dB, 통과 대역에서의 리플(ripple)은 $\pm$ 0.8 dB 및 rejection은 17 dB를 나타내었다.