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A Low Power Current-Steering DAC Selecting Clock Enable Signal  

Yang, Byung-Do (College of Electrical and Computer Engineering, Chungbuk National University)
Min, Jae-Joong (College of Electrical and Computer Engineering, Chungbuk National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.48, no.10, 2011 , pp. 39-45 More about this Journal
Abstract
This paper proposes a low power current-steering 10-bit DAC selecting clock enable signal. The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in wihich the data will not be changed. The proposed DAC was implemented using a 0.13${\mu}m$ CMOS process with $V_{DD}=1.2V$. Its core area is 0.21$mm^2$. It consumes 4.46mW at 1MHz signal frequency and 200MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25MHz and 10MHz signal frequencies, respectively. The measured SFDRs are 72.8dB and 56.1dB at 1MHz and 50MHz signal frequencies, respectively.
Keywords
data-dependant; clock enable signal; digital-to-analog converters (DAC); low-power;
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