1 |
D. A. Mercer, "Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in CMOS," IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1688-1698, Aug. 2007.
DOI
|
2 |
C.-H. Lin et al., "A 12 bit 2.9 GS/s DAC With IM3 < -60 dBc Beyond 1 GHz in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3285-3293, Dec. 2009.
DOI
|
3 |
D.-H. Lee et al., "Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method," IEEE Trans. Circuits Sys. II, Exp. Brief, vol. 56, no. 2, pp. 137-141, Feb. 2009.
DOI
|
4 |
M.-H. Shen et al., "Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC," IEEE Trans. Circuits Sys. II, Exp. Brief, vol. 57, no. 5, pp. 369-373, May 2010.
DOI
|
5 |
J.Bastos et al., "A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC," IEEE J.Solid-State Circuits, vol. 33, no.12, pp. 1959-1969, Dec. 1998.
DOI
ScienceOn
|
6 |
C-H. Lin and K. Bult, "A 10-b, S-MSample/s CMOS DAC in 0.6 mm2," IEEE J.Solid-state Circuits, vol. 33, no.12, pp. 1948-1958, Dec.1998.
DOI
ScienceOn
|
7 |
A. Van den Bosch et al., "A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter," IEEE J.Solid-State Circuits, vol. 36, no.3, pp.315-324, Mar 2001.
DOI
ScienceOn
|
8 |
Y. Cong et al., "A 1.5-V 14-Bit 100-MSample/s Self Calibrated DAC," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2051-2060, Dec. 2003.
DOI
ScienceOn
|
9 |
K. O'Sullivan et al., "A 12-bit 320-MSample/s Current-Steering CMOS D/A Converter in 0.44 mm2," IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1064-2060, July 2004.
DOI
|
10 |
J. A. Starzyk et al., "A Cost-Effective Approach to the Design and Layout of a 14-b Current-Steering DAC Macrocell," IEEE Trans. Circuits Sys. I, Reg. Papers, vol. 51, no. 1, pp. 196-300, Jan. 2004.
DOI
ScienceOn
|
11 |
J. Deveugele et al., "A 10-bit 250-MS/s Binary-Weighted Current- Steering DAC," IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 320-329, Feb. 2006.
DOI
ScienceOn
|