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An 8b 200MHz Time-Interleaved Subranging ADC With a New Reference Voltage Switching Scheme  

Moon, Jung-Woong (Dept. of Electronic Engineering, Sogang University)
Yang, Hee-Suk (Dept. of Electronic Engineering, Sogang University)
Lee, Seung-Hoon (Dept. of Electronic Engineering, Sogang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SC / v.39, no.4, 2002 , pp. 25-35 More about this Journal
Abstract
This work describes an 8b 200MHz time-interleaved subranging analog-to-digital converter (ADC) based on a single-poly digital CMOS process. Two fine ADCs for lower digital bits of the proposed ADC employ a time-sharing double-channel architecture to increase system speed and a new reference voltage switching scheme to reduce settling time of the reference voltages and chip area. The proposed intermeshed resistor string, which generates reference voltages for fine ADCs, improves linearity and settling time of the reference voltages simultaneously. The proposed sample- and-hold amplifier(SHA) is based on a highly linear common-drain amplifier and passive differential circuits to minimize power consumption and chip area with 8b accuracy and employs input dynamic common mode feedback circuits for high dynamic performance at a 200MHz sampling rate. A new encoding circuit in a coarse ADC simplifies the signal processing between the coarse ADC and two successive fine ADCs.
Keywords
ADC; SHA; Reference Switching;
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