• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.1
• /
• pp.56-61
• /
• 2011

This paper describes design of a programmable frequency synthesizer for RF PLL with $0.18{\mu}m$ silicon CMOS technology being used as an application of the UWB system like MBOA. To get good performance of speed and noise super dynamic circuits was used, and to get programmable division ratio switching circuits was used. Especially to solve narrow bandwidth problem of the dynamic circuits load resistance value of unit divider block was varied. Simulation results of the designed circuit shows very fast and wide operation characteristics as 1~14GHz frequency range.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.1
• /
• pp.50-55
• /
• 2011

In this paper, Intermediate frequency tunable 4th order Switched Capacitor(SC) bandpass Sigma-Delta(${\Sigma}-{\Delta}$) modulator using feedback integrator using feedback integrator coefficients is proposed. The center frequency of the modulator can be easily changed than conventional structure because of a number of integrator coefficients which is decided rate of capacitors in circuit is reduced. In addition additive clocks and additive clock generating circuit are not necessary. The purposed modulator was implemented in $0.18{\mu}m$ CMOS technology. The resolution of the modulator within 200 kHz bandwidth and 80 MHz sampling frequency under fin = 15 MHz, 20 MHz, 25 MHz are over 12 bit.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.7
• /
• pp.1552-1558
• /
• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.17 no.2
• /
• pp.355-362
• /
• 2013

A hardware implementation of phase calculator for extracting 3D depth image from TOF(Time-Of-Flight) sensor is described. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. The designed phase calculator is verified by FPGA-in-the-loop verification using MATLAB/Simulink, and synthesized with a TSMC 0.18-${\mu}m$ CMOS cell library. It has 16,000 gates and the estimated throughput is about 9.6 Gbps at 200Mhz@1.8V.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.12
• /
• pp.2716-2724
• /
• 2012

In this paper, a Phase Difference-to-Voltage Converter (PDVC) has been introduced into a conventional fractional-N PLL to suppress fractional spurs. The PDVC controls charge pump current depending on the phase difference of two input signals to phase frequency detector. The charge pump current decreases as the phase difference of two input signals increase. It results in the reduction of fractional spurs in the proposed fractional-N PLL. The proposed fractional-N PLL with PDVC has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.16 no.11
• /
• pp.2495-2502
• /
• 2012

This paper presents a new structure of phase looked loop (PLL) for replacing a process sensitive resistor in loop filter with an additional charge pump (CP). The additional charge pump works as a resistor in a loop filter. The output of two charge pumps changes same direction according to process variation. The simulation results according to process conditions(SS/TT/FF) demonstrate that the proposed PLL works properly with process variations. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by simulation with HSPICE.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.46 no.1
• /
• pp.63-67
• /
• 2009

Current mismatch in a charge pump causes degradation in spectral purity of the phase locked loops(PLLs), such as reference spurs. The current mismatch can be reduced by increasing the output resistance of the charge pump, as in a cascoded output stage. However as the supply voltage is lowered, it is hard to stack transistors. In this paper, a new method for reducing the current mismatch is proposed. The proposed method is based on a feed-forward compensation for the channel length modulation effect of the output stage. The new method has been demonstrated through simulations on typical $0.18{\mu}m$ CMOS circuits.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.6
• /
• pp.63-70
• /
• 2014

A low-N phase-locked loop clock generator with frequency multiplier is proposed to improve phase noise characteristic. Delay-variance voltage converter (DVVC) generates output voltages according to the delay variance of delay stages in voltage controlled oscillator. The output voltages of average circuit with the output voltages of DVVC are applied to the delay stages in VCO to reduce jitter. The HSPICE simulation of the proposed phase-locked loop clock generator with a $0.18{\mu}m$ CMOS process shows an 11.3 ps of peak-to-peak jitter.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.2
• /
• pp.25-33
• /
• 2007

In this paper, a fourth-order single-bit delta-sigma modulator is presented and implemented. The loop-filter is composed of both feedback and feedforward paths. Measurement results show that maximum 99dB dynamic range is achievable at a clock rate of 3.2MHz for 20kHz baseband. The proposed modulator has been fabricated in a $0.18{\mu}m$ standard CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.7
• /
• pp.17-22
• /
• 2012

A novel Clock Generator with jitter suppressed delay-locked loop (DLL) has been proposed to generate highly accurate output signals. The proposed Clock Generator has a VCDL which can suppress its jitter by generating control signals proportional to phase differences among delay stages. It has been designed to generate 1GHz output at 100MHz input with 1.8V $0.18{\mu}m$ CMOS process. The simulation result demonstrates a 3.24ps of peak-to-peak jitter.