• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.816-821
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• 2019

A counter-type time-to-digital converter was designed using a dual edge T flip-flop. The time-to-digital converter was designed with a $0.18{\mu}m$ CMOS process at a supply voltage of 1.5 volts. In a typical time-to-digital converter, when the period of the clock is T, a conversion error corresponding to the period of the clock occurs due to the asynchronism between the input signal and the clock. However, the clock of the time-to-digital converter proposed in this paper is generated in synchronization with the start signal which is the input signal. As a result, conversion errors that may occur due to asynchronization of the start signal and the clock do not occur. The flip-flops constituting the counters are composed of dual-edge flip-flops operating at the positive and negative edges of the clock to improve the resolution.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.7-13
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• 2009

This paper presents a multi-channel transceiver that achieves a data rate of 3.125Gb/s/ch. The LVDS is used because of its noise immunity and low power consumption. And a pre-emphasis circuit is also proposed to increase the transmitter speed. On the receiver side, a low-power CDR(clock and data recovery) using 1/4-rate clock based on dual-interpolator is proposed. The CDR generates needed additional clocks in each recovery part internally using only inverters. Therefore each part can be supplied with the same number of 1/4-rate clocks from a clock generator as in 1/2-rate clock method. Thus, the reduction of a clock frequency relaxes the speed limitation and lowers power dissipation. The prototype chip is comprised of two channels and was fabricated in a $0.18{\mu}m$ standard CMOS process. The output jitter of transmitter is loops, peak-to-peak(0.31UI) and the measured recovered clock jitter is 47.33ps, peak-to-peak which is equivalent to 3.7% of a clock period. The area of the chip is $3.5mm^2$ and the power consumption is about 119mW/ch.

• The Journal of the Korea institute of electronic communication sciences
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• v.14 no.2
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• pp.309-316
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• 2019

In this paper, a low-jitter delay-locked loop that compensates for local clock skew is presented. The proposed DLL consists of a phase splitter, a phase detector(PD), a charge pump, a bias generator, a voltage-controlled delay line(VCDL), and a level converter. The VCDL uses self-biased delay cells using current mode logic(CML) to have insensitive characteristics to temperature and supply noises. The phase splitter generates two reference clocks which are used as the differential inputs of the VCDL. The PD uses the only single clock from the phase splitter because the PD in the proposed circuit uses CMOS logic that consumes less power compared to CML. Therefore, the output of the VCDL is also converted to the rail-to-rail signal by the level converter for the PD as well as the local clock distribution circuit. The proposed circuit has been designed with a $0.13-{\mu}m$ CMOS process. A global CLK with a frequency of 1-GHz is externally applied to the circuit. As a result, after about 19 cycles, the proposed DLL is locked at a point that the control voltage is 597.83mV with the jitter of 1.05ps.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.370-372
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• 2004

본 논문에서는 162bits의 Key Size를 가지고서도 RSA 1024bits의 암호학적 강도를 지니는 스마트카드용으로 적합한 ECC Coprocessor의 구현하고자 한다. ECC의 하드웨어 구현시의 적합성을 위해 162bit Optimal Normal Basis를 선택하였으며, Multiplication은 23 클록 사이클에 수행이 되도록 구현하였으며. Inversion은 Multiplication을 11번 사용하는 알고리즘을 선택하였다. 이때 한번의 점간의 덧셈 연산을 마치는데 331(335) 클록 사이클이 소요되며 클록의 최소주기는 3ns 이다. 또한 Area는 37,111를 기록했다.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.6
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• pp.33-41
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• 2014

In this paper, we propose a D flip-flop based on quantum-dot cellular automata(QCA) clocking and design a programmable quantum-dot cell(QPCA) structure using the proposed D flip-flop. Previous D flip-flops on QCA are that input should be set to an arbitrary value, and wasted output values exist because it was utilized to duplicate by clock pulse and QCA clocking. In order to eliminate these defects, we propose a D flip-flop structure using binary wire and clocking technique on QCA. QPCA structure consists of wire control logic, rule control logic, D flip-flop and XOR logic gate. In experiment, we perform the simulation of QPCA structure using QCADesigner. As the result, we confirm the efficiency of the proposed structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.2
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• pp.408-414
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• 2014

This paper proposes a charge-pump phase-locked loop (PLL) with 51-phase output clock of a 125 MHz target frequency. The proposed PLL uses three voltage controlled oscillators (VCOs) to generate 51-phase clock and increase of maximum operating frequency. The 17 delay-cells consists of each VCO, and a resistor averaging scheme which reduces the phase mismatch among 51-phase clock combines three VCOs. The proposed PLL uses a 65 nm 1-poly 9-metal CMOS process with 1.0 V supply. The simulated peak-to-peak 지터 of output clock is 0.82 ps at an operating frequency of 125 MHz. The differential non-linearity (DNL) and integral non-linearity (INL) of the 51-phase output clock are -0.013/+0.012 LSB and -0.033/+0.041 LSB, respectively. The operating frequency range is 15 to 210 MHz. The area and power consumption of the implemented PLL are $580{\times}160{\mu}m^2$ and 3.48 mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.46 no.2
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• pp.72-77
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• 2009

In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps (CP) and external Loop-Filter(KF). It is adapted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18um 1P6M CMOS process and total chip area excepted LF is $1{\times}1mm^2$. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63mW from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.68-73
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• 2009

This paper describes design and implementation of a spread spectrum clock generator (SSCG) for the DisplayPort. The proposed architecture generates the spread spectrum clock using a sigma-delta fractional-N PLL. The SSCG uses a digital End order MASH 1-1 sigma-delta modulator and a 9bit Up/Dn counter. By using MASH 1-1 sigma-delta modulator, complexity of circuit and chip area can be reduced. The advantage of sigma-delta modulator is the better control over modulation frequency and spread ratio. The SSCG generates dual clock rates which are 270MHz and 162MHz with 0.25% down-spreading and triangular waveform frequency modulation of 33kHz. The peak power reduction is 11.1dBm at 270MHz. The circuit has been designed and fabricated using in 0.18$\mu$m CMOS technology. The chip occupies 0.620mm$\times$0.780mm. The measurement results show that the fabricated chip satisfies the DispalyPort standard.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.