Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Design of DLL-based Low-Power CDR for 2nd-Generation AiPi+ Application

2세대 AiPi+ 용 DLL 기반 저전력 클록-데이터 복원 회로의 설계

  • Park, Joon-Sung (Department of Electronic Engineering, Konkuk University) ;
  • Park, Hyung-Gu (Department of Electronic Engineering, Konkuk University) ;
  • Kim, Seong-Geun (Department of Electronic Engineering, Konkuk University) ;
  • Pu, Young-Gun (Department of Electronic Engineering, Konkuk University) ;
  • Lee, Kang-Yoon (Department of Electronic Engineering, Konkuk University)
  • 박준성 (건국대학교 전자정보통신공학부) ;
  • 박형구 (건국대학교 전자정보통신공학부) ;
  • 김성근 (건국대학교 전자정보통신공학부) ;
  • 부영건 (건국대학교 전자정보통신공학부) ;
  • 이강윤 (건국대학교 전자정보통신공학부)
  • Received : 2010.11.10
  • Accepted : 2011.03.29
  • Published : 2011.04.25
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Abstract

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.

본 논문에서는 패널 내부 인터페이스의 하나인 2세대 AiPi+의 클록-데이터 복원 회로(Clock & Data Recovery)를 제안하였다. 제안하는 클록-데이터 복원 회로의 속도는 기존 AiPi+ 보다 빠른 1.25 Gbps 로 향상되었으며 다중 위상 클록을 생성하기 위하여 Delay-Locked Loop(DLL)를 사용하였다. 본 논문에서는 패널 내부 인터페이스의 저전력, 작은 면적의 이슈를 만족하는 클록-데이터 복원 회로를 설계하였다. 매우 간단한 방법으로 자동적으로 Harmonic-locking 문제를 해결할 수 있는 주파수 검출기 구조를 제안하여 기존 주파수 검출기(Frequency Detector)의 복잡도, 전류 소모, 그리고 외부 인가에 따른 문제를 개선하였으며, 전압 제어 지연 라인(Voltage Controlled Delay Line) 에서 상승/하강 시간 차이에 따른 에지의 사라짐 현상을 막기 위해서 펄스 폭의 최대치를 제한하는 펄스 폭 오류 보정 방법을 사용하였다. 제안하는 클록-데이터 복원 회로는 CMOS 0.18 ${\mu}m$ 공정으로 제작되었으며 면적은 $660\;{\mu}m\;{\times}\;250\;{\mu}m$이고, 공급 전압은 1.8 V이다. Peak-to-Peak 지터는 15 ps, 입력 버퍼, 이퀄라이저, 병렬화기를 제외한 클록-데이터 복원 회로의 소모 전력은 5.94 mW 이다.

Keywords

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